BACPAC

BACPAC, or the Berkeley Advanced Chip Performance Calculator, is a software program to explore the effect of changes in IC technology. The use enters a set of fairly fundamental properties of the technology (such as interconnect layer thickness, and logic depth) and the program estimates the system level performance of an IC built with these assumptions. Previous work in this area can be found in [1] and,[2] but these do not consider many of the effects of deep-sub-micrometre interconnect. BACPAC is based on the work in.[3]

BACPAC uses analytical approximations for system properties such as delay and interconnect requirements. The intent is not absolute accuracy for a given design, but to show trends and effects of technology changes.

Inputs to BACPAC

Interconnect

  • Number of routing layers
  • Pitches (center to center distance of each layer)
  • Resistivity of the wires
  • Dielectric constant of the insulators between the layers

Device

  • Vdd, also called supply voltage
  • Vt, also called threshold voltage
  • Gate oxide thickness of the MOS transistors
  • Drain current
  • Fan-in (number of inputs for each gate, on the average)

System-level

  • Block design size (number of gates in each block)
  • Silicon efficiency (depends on design style - custom, ASIC, gate array, and so on)
  • logic depth (number of gates between state elements)
  • Rent’s exponent (how the number of connections varies with block size - see Rent's rule.)

BACPAC outputs

Delay analysis

  • Chip area
  • Maximum clock frequency - how fast the chip can run
  • Optimized device sizes - estimated devices sizes to make it run this fast
  • Interconnect RC
  • Average wirelength (local & global)
  • Ratio of wire delay to gate delay

Noise analysis

  • Clock frequency with noise
  • Newly optimized device sizes for the clock distribution network
  • Ratio of wire delay to gate delay

Wirability analysis

  • Wiring capacity
  • Wiring requirements (global & local),
  • Wiring needs for clock distribution
  • Wiring needs for the power distribution network

Power analysis

  • Total power consumption, divided into sub-categories:
    • Clock (power needed to distribute the clock across the chip)
    • I/O (power needed to get needed signals on and off the chip)
    • memory (power needed to retain and access data in the internal memories)
    • global wiring (power dissipated in the global wiring)
    • logic (power dissipated in the logic gates themselves)
    • short-circuit (power wasted inside the gates from pull-up and pull down transistors fighting each other during switching)
    • leakage (power that flows through the gate even when it is not switching)

Yield analysis

  • Projected yields for excellent, average, and poor process control using a negative binomial yield mode

References
  1. H.B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, Chapter 9, 1990.
  2. G.A. Sai-Halasz, “Performance trends in high-performance processors,” Proc. IEEE, pp. 20–36, Jan. 1995.
  3. D. Sylvester and K. Keutzer, “Getting to the bottom of deep submicron,” Proc. of International Conference on CAD, pp. 203–211, 1998.
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