BMS-203

CER-203 is a central unit of early digital computer developed by Mihajlo Pupin Institute (Serbia) in 1971. It contained both central processing unit and primary memory.

CER-203: CPU testing

Specifications

Central Processing Unit:

Number of instructions: 32
Performance:
- one 16-cycle instruction: 20 μs
- one single cycle instruction: 5 μs
- addition and/or subtraction of two 15-digit numbers: 20 μs

Primary memory:

Capacity: 8 kilowords
Speed (cycle time): 1 μs
Complete, autonomous memory error checking
Parity control

See also

CER-203 computer
CER Computers
Mihajlo Pupin Institute
History of computer hardware in the SFRY

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