Source-synchronous
Source-Synchronous clocking refers to a technique used for timing symbols on a digital interface. Specifically, it refers to the technique of having the transmitting device send a clock signal along with the data signals. The timing of the unidirectional data signals is referenced to the clock (often called the strobe) sourced by the same device that generates those signals, and not to a global clock (i.e. generated by a bus master). Compared to other digital clocking topologies like system-synchronous clocks, where a global clock source is fed to all devices in the system, a source-synchronous clock topology can attain far higher speeds.
This type of clocking is common in high-speed interfaces between micro-chips, including DDR SDRAM, SGI XIO interface, Intel Front Side Bus for the x86 and Itanium processors, HyperTransport, SPI-4.2 and many others.
Reasons for usage
A reason that source-synchronous clocking is useful is that it has been observed that all of the circuits within a given semiconductor device experience roughly the same process-voltage-temperature (PVT) variation. This means signal propagation delay experienced by the data through a device tracks the delay experienced by the clock through that same device over PVT. This advantage allows higher speed operation as compared to the traditional technique of providing the clock from a third device to both the transmitter and the receiver. Another benefit is that higher complexity data-recovery or clock-data-recovery circuits (such as PLLs) are not required when this technique is used.
Or rather than higher clock speeds, large systems that take advantage of source-synchronous clocking can have the benefit of a higher tolerance of PVT variation of its individual components.
Timing Analysis
Synchronous logic elements such as flip-flops have static timing criteria that must be satisfied in order for them to work correctly. In a system-synchronous clock topology where a skew-aligned clock is fed to all devices, the criteria are
A source-synchronous clock topology eliminates two of these factors, and . The former is eliminated since both clock and data signals are driven by identical flip-flops on the same silicon at the same temperature and voltage, thereby equalizing the seen by both clock and data. The latter is eliminated for the same reason - since the clock and data are driven by identical devices and (ideally) connected with wires of equal length, the skew between clock and data is greatly reduced. For this reason, can be reduced significantly. Since frequency is inversely proportional to clock period, the clock frequency increases as a result.
Drawbacks
One drawback of using source-synchronous clocking is the creation of a separate clock-domain at the receiving device, namely the clock-domain of the strobe generated by the transmitting device. This strobe clock-domain is often not synchronous to the core clock domain of the receiving device. For proper operation of the received data with other data already present in the device, an additional stage of synchronization logic is required to transfer the received data into the core clock-domain of the receiving device. This stage can often be found alongside source synchronous logic. This usually results in greater system complexity compared to globally clocked systems, but the benefits are generally much greater than this increase in complexity.
Implementation Variations
In bi-directional data transfer buses, two opposing unidirectional strobes can be sent from each device. Often the strobe is free running in this case. That is, the strobe continues to toggle whether there is data being transferred or not.
Another variation is the sharing of the same bus to transfer the strobe. In this case the strobe can only be transferred by the device that is sending the data and may require transmission of pre-ambles and post-ambles to indicate the start and end of the strobes. (Example: DDR2).
In large ASICs or processors, multiple strobes and data groups (data bits that are associated to the same strobe) may exist between the same two devices to account for the slightly different PVT variations in different regions of the same die.