Sparcle

The Sparcle is an experimental 32-bit microprocessor chip developed in 1992 by a consortium of MIT, LSI Corporation, and Sun Microsystems. It was an evolution Sun's SPARC RISC architecture with features geared towards "large-scale multiprocessing".[1] The chip was manufactured by LSI.

Besides these enhancements the Sparcle was otherwise unremarkable, incorporating 200,000 transistors and dissipating two watts. It included no cache and had a clock speed of less than 40 MHz. The new features included:

Features to tolerate and synchronize memory and communications latencies
Features supporting fine-grained synchronization
Features to initiate actions on remote processors and quickly respond to asynchronous events

The Sparcle was used to build the experimental Alewife computer at MIT.

References

Agarwal, Anant; et al. (June 1993). "Sparcle: An Evolutionary Processor Design for Large-scale Multiprocessors" (PDF). IEEE Micro. 13 (3): 48–61. Retrieved Feb 5, 2020.

External links

Šilc, Jurij; et al. (1999). Processor Architecture: From Dataflow to Superscalar and Beyond. Springer Science & Business Media. p. 272. ISBN 3-540-64798-8. Retrieved Feb 5, 2020.
Iannucci, Robert A.; et al. (1994). Multithreaded Computer Architecture: A Summary of the State of the ART. Springer Science & Business Media. p. 163. ISBN 0-7923-9477-1. Retrieved Feb 5, 2020.

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[Agarwal-1] Agarwal, Anant; et al. (June 1993). "Sparcle: An Evolutionary Processor Design for Large-scale Multiprocessors" (PDF). IEEE Micro. 13 (3): 48–61. Retrieved Feb 5, 2020.