SuperSPARC

The SuperSPARC is a microprocessor that implements the SPARC V8 instruction set architecture (ISA) developed by Sun Microsystems. 33 and 40 MHz versions were introduced in 1992. The SuperSPARC contained 3.1 million transistors. It was fabricated by Texas Instruments (TI) at Miho, Japan in a 0.8 micrometre triple-metal[1] BiCMOS process.[2]

SuperSPARC
The SuperSPARC microprocessor
General information
Launched1992
Discontinued1995
Designed bySun Microsystems
Common manufacturer(s)
Performance
Max. CPU clock rate33 MHz to 90 MHz
Cache
L2 cachenone, 1 MB, 2 MB
Architecture and classification
Instruction setSPARC V8
Physical specifications
Transistors
  • 3.1 million
Cores
  • 1

There were two derivatives of the SuperSPARC: the SuperSPARC+ and SuperSPARC-II. The SuperSPARC+ was developed to remedy some of the design flaws that limited the SuperSPARC's clock frequency and thus performance. The SuperSPARC-II, introduced in 1994, was a major revision with improvements that enabled the microprocessor to reach 85 MHz in desktop systems and 90 MHz in the more heavily cooled SPARCserver-1000E.

The SuperSPARC-II was replaced in 1995 by the 64-bit UltraSPARC, an implementation of the 64-bit SPARC V9 ISA.


Models

SuperSPARC (Viking)

ModelCPUL2 CacheClock SpeedBus SpeedNotes
SM201 CPUnone33 MHz33 MHz
SM211 CPU1 MB33 MHz33 MHzonly works in early SPARCserver-2000 systems
SM301 CPUnone36 MHz36 MHz
SM401 CPUnone40 MHz40 MHz
SM411 CPU1 MB40.3 MHz40 MHz
SM501 CPUnone50 MHz50 MHz
SM511 CPU1 MB50 MHz40 MHz
SM51-21 CPU2 MB50 MHz40 MHz
SM522 CPU1 MB45 MHz40 MHz
SM52X2 CPU1 MB50 MHz40 MHz
SM611 CPU1 MB60 MHz50/55 MHz
SM61-21 CPU2 MB60 MHz50/55 MHz

SuperSPARC II (Voyager)

ModelCPUL2 CacheClock SpeedBus SpeedNotes
SM711 CPU1 MB75 MHz50 MHz
SM811 CPU1 MB85 MHz50 MHz
SM81-21 CPU2 MB85 MHz50/55 MHz
SM91-21 CPU2 MB90 MHz50 MHz

References

  • "TI SuperSPARC for Sun Station 3 in production". (11 May 1992). Electronic News.
  • DeTar, Jim (10 October 1994). "Sun sets SuperSPARC-II as UltraSPARC V9 bridge". Electronic News.
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