x86 instruction listings

The x86 instruction set refers to the set of instructions that x86-compatible microprocessors support. The instructions are usually part of an executable program, often stored as a computer file and executed on the processor.

The x86 instruction set has been extended several times, introducing wider registers and datatypes as well as new functionality.[1]

x86 integer instructions

This is the full 8086/8088 instruction set of Intel. Most if not all of these instructions are available in 32-bit mode; they just operate on 32-bit registers (eax, ebx, etc.) and values instead of their 16-bit (ax, bx, etc.) counterparts. See also x86 assembly language for a quick tutorial for this processor family. The updated instruction set is also grouped according to architecture (i386, i486, i686) and more generally is referred to as x86 32 and x86 64 (also known as AMD64).

Original 8086/8088 instructions
Original 8086/8088 instruction set
InstructionMeaningNotesOpcode
AAAASCII adjust AL after additionused with unpacked binary coded decimal0x37
AADASCII adjust AX before division8086/8088 datasheet documents only base 10 version of the AAD instruction (opcode 0xD5 0x0A), but any other base will work. Later Intel's documentation has the generic form too. NEC V20 and V30 (and possibly other NEC V-series CPUs) always use base 10, and ignore the argument, causing a number of incompatibilities0xD5
AAMASCII adjust AX after multiplicationOnly base 10 version (Operand is 0xA) is documented, see notes for AAD0xD4
AASASCII adjust AL after subtraction0x3F
ADCAdd with carrydestination = destination + source + carry_flag0x10…0x15, 0x80…0x81/2, 0x82…0x83/2 (since 80186)
ADDAdd(1) r/m += r/imm; (2) r += m/imm;0x00…0x05, 0x80/0…0x81/0, 0x82/0…0x83/0 (since 80186)
ANDLogical AND(1) r/m &= r/imm; (2) r &= m/imm;0x20…0x25, 0x80…0x81/4, 0x82…0x83/4 (since 80186)
CALLCall procedurepush eip; eip points to the instruction directly after the call0x9A, 0xE8, 0xFF/2, 0xFF/3
CBWConvert byte to word0x98
CLCClear carry flagCF = 0;0xF8
CLDClear direction flagDF = 0;0xFC
CLIClear interrupt flagIF = 0;0xFA
CMCComplement carry flag0xF5
CMPCompare operands0x38…0x3D, 0x80…0x81/7, 0x82…0x83/7 (since 80186)
CMPSBCompare bytes in memory0xA6
CMPSWCompare words0xA7
CWDConvert word to doubleword0x99
DAADecimal adjust AL after addition(used with packed binary coded decimal)0x27
DASDecimal adjust AL after subtraction0x2F
DECDecrement by 10x48…0x4F, 0xFE/1, 0xFF/1
DIVUnsigned divide(1) AX = DX:AX / r/m; resulting DX = remainder (2) AL = AX / r/m; resulting AH = remainder0xF7/6, 0xF6/6
ESCUsed with floating-point unit0xD8..0xDF
HLTEnter halt state0xF4
IDIVSigned divide(1) AX = DX:AX / r/m; resulting DX = remainder (2) AL = AX / r/m; resulting AH = remainder0xF7/7, 0xF6/7
IMULSigned multiply(1) DX:AX = AX * r/m; (2) AX = AL * r/m0x69, 0x6B (both since 80186), 0xF7/5, 0xF6/5, 0x0FAF (since 80386)
INInput from port(1) AL = port[imm]; (2) AL = port[DX]; (3) AX = port[imm]; (4) AX = port[DX];0xE4, 0xE5, 0xEC, 0xED
INCIncrement by 10x40…0x47, 0xFE/0, 0xFF/0
INTCall to interrupt0xCC, 0xCD
INTOCall to interrupt if overflow0xCE
IRETReturn from interrupt0xCF
JccJump if condition(JA, JAE, JB, JBE, JC, JE, JG, JGE, JL, JLE, JNA, JNAE, JNB, JNBE, JNC, JNE, JNG, JNGE, JNL, JNLE, JNO, JNP, JNS, JNZ, JO, JP, JPE, JPO, JS, JZ)0x70…0x7F, 0x0F80…0x0F8F (since 80386)
JCXZJump if CX is zero0xE3
JMPJump0xE9…0xEB, 0xFF/4, 0xFF/5
LAHFLoad FLAGS into AH register0x9F
LDSLoad pointer using DS0xC5
LEALoad Effective Address0x8D
LESLoad ES with pointer0xC4
LOCKAssert BUS LOCK# signal(for multiprocessing)0xF0
LODSBLoad string byteif (DF==0) AL = *SI++; else AL = *SI--;0xAC
LODSWLoad string wordif (DF==0) AX = *SI++; else AX = *SI--;0xAD
LOOP/LOOPxLoop control(LOOPE, LOOPNE, LOOPNZ, LOOPZ) if (x && --CX) goto lbl;0xE0…0xE2
MOVMovecopies data from one location to another, (1) r/m = r; (2) r = r/m;0xA0...0xA3
MOVSBMove byte from string to string
if (DF==0) 
  *(byte*)DI++ = *(byte*)SI++; 
else 
  *(byte*)DI-- = *(byte*)SI--;
0xA4
MOVSWMove word from string to string
if (DF==0) 
  *(word*)DI++ = *(word*)SI++; 
else 
  *(word*)DI-- = *(word*)SI--;
0xA5
MULUnsigned multiply(1) DX:AX = AX * r/m; (2) AX = AL * r/m;0xF7/4, 0xF6/4
NEGTwo's complement negationr/m *= -1;0xF6/3…0xF7/3
NOPNo operationopcode equivalent to XCHG EAX, EAX0x90
NOTNegate the operand, logical NOTr/m ^= -1;0xF6/2…0xF7/2
ORLogical OR(1) r/m |= r/imm; (2) r |= m/imm;0x08…0x0D, 0x80…0x81/1, 0x82…0x83/1 (since 80186)
OUTOutput to port(1) port[imm] = AL; (2) port[DX] = AL; (3) port[imm] = AX; (4) port[DX] = AX;0xE6, 0xE7, 0xEE, 0xEF
POPPop data from stackr/m = *SP++; POP CS (opcode 0x0F) works only on 8086/8088. Later CPUs use 0x0F as a prefix for newer instructions.0x07, 0x0F(8086/8088 only), 0x17, 0x1F, 0x58…0x5F, 0x8F/0
POPFPop FLAGS register from stackFLAGS = *SP++;0x9D
PUSHPush data onto stack*--SP = r/m;0x06, 0x0E, 0x16, 0x1E, 0x50…0x57, 0x68, 0x6A (both since 80186), 0xFF/6
PUSHFPush FLAGS onto stack*--SP = FLAGS;0x9C
RCLRotate left (with carry)0xC0…0xC1/2 (since 80186), 0xD0…0xD3/2
RCRRotate right (with carry)0xC0…0xC1/3 (since 80186), 0xD0…0xD3/3
REPxxRepeat MOVS/STOS/CMPS/LODS/SCAS(REP, REPE, REPNE, REPNZ, REPZ)0xF2, 0xF3
RETReturn from procedureNot a real instruction. The assembler will translate these to a RETN or a RETF depending on the memory model of the target system.
RETNReturn from near procedure0xC2, 0xC3
RETFReturn from far procedure0xCA, 0xCB
ROLRotate left0xC0…0xC1/0 (since 80186), 0xD0…0xD3/0
RORRotate right0xC0…0xC1/1 (since 80186), 0xD0…0xD3/1
SAHFStore AH into FLAGS0x9E
SALShift Arithmetically left (signed shift left)(1) r/m <<= 1; (2) r/m <<= CL;0xC0…0xC1/4 (since 80186), 0xD0…0xD3/4
SARShift Arithmetically right (signed shift right)(1) (signed) r/m >>= 1; (2) (signed) r/m >>= CL;0xC0…0xC1/7 (since 80186), 0xD0…0xD3/7
SBBSubtraction with borrowalternative 1-byte encoding of SBB AL, AL is available via undocumented SALC instruction0x18…0x1D, 0x80…0x81/3, 0x82…0x83/3 (since 80186)
SCASBCompare byte string0xAE
SCASWCompare word string0xAF
SHLShift left (unsigned shift left)0xC0…0xC1/4 (since 80186), 0xD0…0xD3/4
SHRShift right (unsigned shift right)0xC0…0xC1/5 (since 80186), 0xD0…0xD3/5
STCSet carry flagCF = 1;0xF9
STDSet direction flagDF = 1;0xFD
STISet interrupt flagIF = 1;0xFB
STOSBStore byte in stringif (DF==0) *ES:DI++ = AL; else *ES:DI-- = AL;0xAA
STOSWStore word in stringif (DF==0) *ES:DI++ = AX; else *ES:DI-- = AX;0xAB
SUBSubtraction(1) r/m -= r/imm; (2) r -= m/imm;0x28…0x2D, 0x80…0x81/5, 0x82…0x83/5 (since 80186)
TESTLogical compare (AND)(1) r/m & r/imm; (2) r & m/imm;0x84, 0x84, 0xA8, 0xA9, 0xF6/0, 0xF7/0
WAITWait until not busyWaits until BUSY# pin is inactive (used with floating-point unit)0x9B
XCHGExchange datar :=: r/m; A spinlock typically uses xchg as an atomic operation. (coma bug).0x86, 0x87, 0x91…0x97
XLATTable look-up translationbehaves like MOV AL, [BX+AL]0xD7
XORExclusive OR(1) r/m ^= r/imm; (2) r ^= m/imm;0x30…0x35, 0x80…0x81/6, 0x82…0x83/6 (since 80186)

Added with 80186/80188
InstructionMeaningNotes
BOUNDCheck array index against boundsraises software interrupt 5 if test fails
ENTEREnter stack frameModifies stack for entry to procedure for high level language. Takes two operands: the amount of storage to be allocated on the stack and the nesting level of the procedure.
INSInput from port to stringequivalent to: 
IN (E)AX, DX
MOV ES:[(E)DI], (E)AX
; adjust (E)DI according to operand size and DF
LEAVELeave stack frameReleases the local stack storage created by the previous ENTER instruction.
OUTSOutput string to portequivalent to: 
MOV (E)AX, DS:[(E)SI]
OUT DX, (E)AX
; adjust (E)SI according to operand size and DF
POPAPop all general purpose registers from stackequivalent to: 
POP DI
POP SI
POP BP
POP AX ; no POP SP here, all it does is ADD SP, 2 (since AX will be overwritten later)
POP BX
POP DX
POP CX
POP AX
PUSHAPush all general purpose registers onto stackequivalent to: 
PUSH AX
PUSH CX
PUSH DX
PUSH BX
PUSH SP ; The value stored is the initial SP value
PUSH BP
PUSH SI
PUSH DI
PUSH immediatePush an immediate byte/word value onto the stackexample: 
PUSH 12h
PUSH 1200h
IMUL immediateSigned multiplication of immediate byte/word valueexample: 
IMUL BX,12h
IMUL DX,1200h
IMUL CX, DX, 12h
IMUL BX, SI, 1200h
IMUL DI, word ptr [BX+SI], 12h
IMUL SI, word ptr [BP-4], 1200h
SHL/SHR/SAL/SAR/ROL/ROR/RCL/RCR immediateRotate/shift bits with an immediate value greater than 1example: 
ROL AX,3
SHR BL,3

Added with 80286
InstructionMeaningNotes
ARPLAdjust RPL field of selector
CLTSClear task-switched flag in register CR0
LARLoad access rights byte
LGDTLoad global descriptor table
LIDTLoad interrupt descriptor table
LLDTLoad local descriptor table
LMSWLoad machine status word
LOADALLLoad all CPU registers, including internal ones such as GDTUndocumented, 80286 and 80386 only
LSLLoad segment limit
LTRLoad task register
SGDTStore global descriptor table
SIDTStore interrupt descriptor table
SLDTStore local descriptor table
SMSWStore machine status word
STRStore task register
VERRVerify a segment for reading
VERWVerify a segment for writing

Added with 80386
InstructionMeaningNotes
BSFBit scan forward
BSRBit scan reverse
BTBit test
BTCBit test and complement
BTRBit test and reset
BTSBit test and set
CDQConvert double-word to quad-wordSign-extends EAX into EDX, forming the quad-word EDX:EAX. Since (I)DIV uses EDX:EAX as its input, CDQ must be called after setting EAX if EDX is not manually initialized (as in 64/32 division) before (I)DIV.
CMPSDCompare string double-wordCompares ES:[(E)DI] with DS:[(E)SI] and increments or decrements both (E)DI and (E)SI, depending on DF; can be prefixed with REP
CWDEConvert word to double-wordUnlike CWD, CWDE sign-extends AX to EAX instead of AX to DX:AX
IBTSInsert Bit Stringdiscontinued with B1 step of 80386
INSDInput from port to string double-word
IRETxInterrupt return; D suffix means 32-bit return, F suffix means do not generate epilogue code (i.e. LEAVE instruction)Use IRETD rather than IRET in 32-bit situations
JECXZJump if ECX is zero
LFS, LGSLoad far pointer
LSSLoad stack segment
LODSDLoad string double-wordEAX = *ES:EDI±±; (±± depends on DF, ES cannot be overridden); can be prefixed with REP
LOOPW, LOOPccWLoop, conditional loopSame as LOOP, LOOPcc for earlier processors
LOOPD, LOOPccDLoop while equalif (cc && --ECX) goto lbl;, cc = Z(ero), E(qual), NonZero, N(on)E(qual)
MOV to/from CR/DR/TRMove to/from special registersCR=control registers, DR=debug registers, TR=test registers (up to 80486)
MOVSDMove string double-word*(dword*)ES:EDI±± = *(dword*)ESI±±; (±± depends on DF); can be prefixed with REP
MOVSXMove with sign-extension(long)r = (signed char) r/m; and similar
MOVZXMove with zero-extension(long)r = (unsigned char) r/m; and similar
OUTSDOutput to port from string double-word port[DX] = *(long*)ESI±±; (±± depends on DF)
POPADPop all double-word (32-bit) registers from stackDoes not pop register ESP off of stack
POPFDPop data into EFLAGS register
PUSHADPush all double-word (32-bit) registers onto stack
PUSHFDPush EFLAGS register onto stack
SCASDScan string data double-wordCompares ES:[(E)DI] with EAX and increments or decrements (E)DI, depending on DF; can be prefixed with REP
SETccSet byte to one on condition, zero otherwise(SETA, SETAE, SETB, SETBE, SETC, SETE, SETG, SETGE, SETL, SETLE, SETNA, SETNAE, SETNB, SETNBE, SETNC, SETNE, SETNG, SETNGE, SETNL, SETNLE, SETNO, SETNP, SETNS, SETNZ, SETO, SETP, SETPE, SETPO, SETS, SETZ)
SHLDShift left double-word
SHRDShift right double-wordr1 = r1>>CL ∣ r2<<(32-CL); Instead of CL, immediate 1 can be used
STOSDStore string double-word*ES:EDI±± = EAX; (±± depends on DF, ES cannot be overridden); can be prefixed with REP
XBTSExtract Bit Stringdiscontinued with B1 step of 80386

Added with 80486
InstructionMeaningNotes
BSWAPByte Swapr = r<<24 | r<<8&0x00FF0000 | r>>8&0x0000FF00 | r>>24; Only defined for 32-bit registers. Usually used to change between little endian and big endian representations. When used with 16-bit registers produces various different results on 486,[2] 586, and Bochs/QEMU.[3]
CMPXCHGatomic CoMPare and eXCHanGeSee Compare-and-swap / on later 80386 as undocumented opcode available
INVDInvalidate Internal CachesFlush internal caches
INVLPGInvalidate TLB EntryInvalidate TLB Entry for page that contains data specified
WBINVDWrite Back and Invalidate CacheWrites back all modified cache lines in the processor's internal cache to main memory and invalidates the internal caches.
XADDeXchange and ADDExchanges the first operand with the second operand, then loads the sum of the two values into the destination operand.

Added with Pentium
InstructionMeaningNotes
CPUIDCPU IDentificationReturns data regarding processor identification and features, and returns data to the EAX, EBX, ECX, and EDX registers. Instruction functions specified by the EAX register.[1] This was also added to later 80486 processors
CMPXCHG8BCoMPare and eXCHanGe 8 bytesCompare EDX:EAX with m64. If equal, set ZF and load ECX:EBX into m64. Else, clear ZF and load m64 into EDX:EAX.
RDMSRReaD from Model-specific registerLoad MSR specified by ECX into EDX:EAX
RDTSCReaD Time Stamp CounterReturns the number of processor ticks since the processor being "ONLINE" (since the last power on of system)
WRMSRWRite to Model-Specific RegisterWrite the value in EDX:EAX to MSR specified by ECX
RSM[4] Resume from System Management Mode This was introduced by the i386SL and later and is also in the i486SL and later. Resumes from System Management Mode (SMM)

Added with Pentium MMX
InstructionMeaningNotes
RDPMCRead the PMC [Performance Monitoring Counter]Specified in the ECX register into registers EDX:EAX

Also MMX registers and MMX support instructions were added. They are usable for both integer and floating point operations, see below.

Added with AMD K6
InstructionMeaningNotes
SYSCALLfunctionally equivalent to SYSENTER
SYSRETfunctionally equivalent to SYSEXIT

AMD changed the CPUID detection bit for this feature from the K6-II on.

Added with Pentium Pro
InstructionMeaningNotes
CMOVccConditional move(CMOVA, CMOVAE, CMOVB, CMOVBE, CMOVC, CMOVE, CMOVG, CMOVGE, CMOVL, CMOVLE, CMOVNA, CMOVNAE, CMOVNB, CMOVNBE, CMOVNC, CMOVNE, CMOVNG, CMOVNGE, CMOVNL, CMOVNLE, CMOVNO, CMOVNP, CMOVNS, CMOVNZ, CMOVO, CMOVP, CMOVPE, CMOVPO, CMOVS, CMOVZ)
UD2Undefined InstructionGenerates an invalid opcode exception. This instruction is provided for software testing to explicitly generate an invalid opcode. The opcode for this instruction is reserved for this purpose.

Added with Pentium II
InstructionMeaningNotes
SYSENTERSYStem call ENTERSometimes called the Fast System Call instruction, this instruction was intended to increase the performance of operating system calls. Note that on the Pentium Pro, the CPUID instruction incorrectly reports these instructions as available.
SYSEXITSYStem call EXIT

Added with SSE
InstructionOpcodeMeaningNotes
NOP r/m160F 1F /0Multi-byte no-operation instruction.
NOP r/m32
PREFETCHT00F 18 /1Prefetch Data from AddressPrefetch into all cache levels
PREFETCHT10F 18 /2Prefetch Data from AddressPrefetch into all cache levels EXCEPT[5][6] L1
PREFETCHT20F 18 /3Prefetch Data from AddressPrefetch into all cache levels EXCEPT L1 and L2
PREFETCHNTA0F 18 /0Prefetch Data from AddressPrefetch to non-temporal cache structure, minimizing cache pollution.
SFENCE0F AE F8Store FenceProcessor hint to make sure all store operations that took place prior to the SFENCE call are globally visible

Added with SSE2
InstructionOpcodeMeaningNotes
CLFLUSH m80F AE /7Cache Line FlushInvalidates the cache line that contains the linear address specified with the source operand from all levels of the processor cache hierarchy
LFENCE0F AE E8Load FenceSerializes load operations.
MFENCE0F AE F0Memory FencePerforms a serializing operation on all load and store instructions that were issued prior the MFENCE instruction.
MOVNTI m32, r320F C3 /rMove Doubleword Non-TemporalMove doubleword from r32 to m32, minimizing pollution in the cache hierarchy.
PAUSEF3 90Spin Loop HintProvides a hint to the processor that the following code is a spin loop, for cacheability

Added with SSE3
InstructionMeaningNotes
MONITOR EAX, ECX, EDXSetup Monitor AddressSets up a linear address range to be monitored by hardware and activates the monitor.
MWAIT EAX, ECXMonitor WaitProcessor hint to stop instruction execution and enter an implementation-dependent optimized state until occurrence of a class of events.

Added with SSE4.2
InstructionOpcodeMeaningNotes
CRC32 r32, r/m8F2 0F 38 F0 /rAccumulate CRC32Computes CRC value using the CRC-32C (Castagnoli) polynomial 0x11EDC6F41 (normal form 0x1EDC6F41). This is the polynomial used in iSCSI. In contrast to the more popular one used in Ethernet, its parity is even, and it can thus detect any error with an odd number of changed bits.
CRC32 r32, r/m8F2 REX 0F 38 F0 /r
CRC32 r32, r/m16F2 0F 38 F1 /r
CRC32 r32, r/m32F2 0F 38 F1 /r
CRC32 r64, r/m8F2 REX.W 0F 38 F0 /r
CRC32 r64, r/m64F2 REX.W 0F 38 F1 /r
CRC32 r32, r/m8F2 0F 38 F0 /r

Added with x86-64
InstructionMeaningNotes
CDQESign extend EAX into RAX
CQOSign extend RAX into RDX:RAX
CMPSQCoMPare String Quadword
CMPXCHG16BCoMPare and eXCHanGe 16 Bytes
IRETQ64-bit Return from Interrupt
JRCXZJump if RCX is zero
LODSQLoaD String Quadword
MOVSXDMOV with Sign Extend 32-bit to 64-bit
POPFQPOP RFLAGS Register
PUSHFQPUSH RFLAGS Register
RDTSCPReaD Time Stamp Counter and Processor ID
SCASQSCAn String Quadword
STOSQSTOre String Quadword
SWAPGSExchange GS base with KernelGSBase MSR

Added with AMD-V
InstructionMeaningNotesOpcode
CLGIClear Global Interrupt FlagClears the GIF0x0F 0x01 0xDD
INVLPGAInvalidate TLB entry in a specified ASIDInvalidates the TLB mapping for the virtual page specified in RAX and the ASID specified in ECX.0x0F 0x01 0xDF
MOV(CRn)Move to or from control registersMoves 32- or 64-bit contents to control register and vice versa.0x0F 0x22 or 0x0F 0x20
MOV(DRn)Move to or from debug registersMoves 32- or 64-bit contents to control register and vice versa.0x0F 0x21 or 0x0F 0x23
SKINITSecure Init and Jump with AttestationVerifiable startup of trusted software based on secure hash comparison0x0F 0x01 0xDE
STGISet Global Interrupt FlagSets the GIF.0x0F 0x01 0xDC
VMLOADLoad state From VMCBLoads a subset of processor state from the VMCB specified by the physical address in the RAX register.0x0F 0x01 0xDA
VMMCALLCall VMMUsed exclusively to communicate with VMM0x0F 0x01 0xD9
VMRUNRun virtual machinePerforms a switch to the guest OS.0x0F 0x01 0xD8
VMSAVESave state To VMCBSaves additional guest state to VMCB.0x0F 0x01 0xDB

Added with Intel VT-x
InstructionMeaningNotesOpcode
INVEPTInvalidate Translations Derived from EPTInvalidates EPT-derived entries in the TLBs and paging-structure caches.0x66 0x0F 0x38 0x80
INVVPIDInvalidate Translations Based on VPIDInvalidates entries in the TLBs and paging-structure caches based on VPID.0x66 0x0F 0x38 0x80
VMFUNCInvoke VM functionInvoke VM function specified in EAX.0x0F 0x01 0xD4
VMPTRLDLoad Pointer to Virtual-Machine Control StructureLoads the current VMCS pointer from memory.0x0F 0xC7/6
VMPTRSTStore Pointer to Virtual-Machine Control StructureStores the current-VMCS pointer into a specified memory address. The operand of this instruction is always 64 bits and is always in memory.0x0F 0xC7/7
VMCLEARClear Virtual-Machine Control StructureWrites any cached data to the VMCS0x66 0x0F 0xC7/6
VMREADRead Field from Virtual-Machine Control StructureReads out a field in the VMCS0x0F 0x78
VMWRITEWrite Field to Virtual-Machine Control StructureModifies a field in the VMCS0x0F 0x79
VMCALLCall to VM MonitorCalls VM Monitor function from Guest System0x0F 0x01 0xC1
VMLAUNCHLaunch Virtual MachineLaunch virtual machine managed by current VMCS0x0F 0x01 0xC2
VMRESUMEResume Virtual MachineResume virtual machine managed by current VMCS0x0F 0x01 0xC3
VMXOFFLeave VMX OperationStops hardware supported virtualisation environment0x0F 0x01 0xC4
VMXONEnter VMX OperationEnters hardware supported virtualisation environment0xF3 0x0F 0xC7/6

Added with ABM

LZCNT, POPCNT (POPulation CouNT) – advanced bit manipulation

Added with BMI1

ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT

Added with BMI2

BZHI, MULX, PDEP, PEXT, RORX, SARX, SHRX, SHLX

Added with TBM

AMD introduced TBM together with BMI1 in its Piledriver[7] line of processors; later AMD Jaguar and Zen-based processors do not support TBM.[8] No Intel processors (as of 2020) support TBM.

Instruction Description[9] Equivalent C expression[10]
BEXTR Bit field extract (with immediate) (src >> start) & ((1 << len) - 1)
BLCFILL Fill from lowest clear bit x & (x + 1)
BLCI Isolate lowest clear bit ~(x + 1)
BLCIC Isolate lowest clear bit and complement ~x & (x + 1)
BLCMSK Mask from lowest clear bit x ^ (x + 1)
BLCS Set lowest clear bit (x + 1)
BLSFILL Fill from lowest set bit (x - 1)
BLSIC Isolate lowest set bit and complement (x - 1)
T1MSKC Inverse mask from trailing ones (x + 1)
TZMSK Mask from trailing zeros ~x & (x - 1)

Added with CLMUL instruction set
InstructionOpcodeDescription
PCLMULQDQ xmmreg,xmmrm,imm66 0f 3a 44 /r ib Perform a carry-less multiplication of two 64-bit polynomials over the finite field GF(2k).
PCLMULLQLQDQ xmmreg,xmmrm66 0f 3a 44 /r 00 Multiply the low halves of the two registers.
PCLMULHQLQDQ xmmreg,xmmrm66 0f 3a 44 /r 01 Multiply the high half of the destination register by the low half of the source register.
PCLMULLQHQDQ xmmreg,xmmrm66 0f 3a 44 /r 10 Multiply the low half of the destination register by the high half of the source register.
PCLMULHQHQDQ xmmreg,xmmrm66 0f 3a 44 /r 11 Multiply the high halves of the two registers.

Added with Intel ADX
InstructionDescription
ADCXAdds two unsigned integers plus carry, reading the carry from the carry flag and if necessary setting it there. Does not affect other flags than the carry.
ADOXAdds two unsigned integers plus carry, reading the carry from the overflow flag and if necessary setting it there. Does not affect other flags than the overflow.

x87 floating-point instructions

Original 8087 instructions
InstructionMeaningNotes
F2XM1more precise than for x close to zero
FABSAbsolute value
FADDAdd
FADDPAdd and pop
FBLDLoad BCD
FBSTPStore BCD and pop
FCHSChange sign
FCLEXClear exceptions
FCOMCompare
FCOMPCompare and pop
FCOMPPCompare and pop twice
FDECSTPDecrement floating point stack pointer
FDISIDisable interrupts8087 only, otherwise FNOP
FDIVDividePentium FDIV bug
FDIVPDivide and pop
FDIVRDivide reversed
FDIVRPDivide reversed and pop
FENIEnable interrupts8087 only, otherwise FNOP
FFREEFree register
FIADDInteger add
FICOMInteger compare
FICOMPInteger compare and pop
FIDIVInteger divide
FIDIVRInteger divide reversed
FILDLoad integer
FIMULInteger multiply
FINCSTPIncrement floating point stack pointer
FINITInitialize floating point processor
FISTStore integer
FISTPStore integer and pop
FISUBInteger subtract
FISUBRInteger subtract reversed
FLDFloating point load
FLD1Load 1.0 onto stack
FLDCWLoad control word
FLDENVLoad environment state
FLDENVWLoad environment state, 16-bit
FLDL2ELoad log2(e) onto stack
FLDL2TLoad log2(10) onto stack
FLDLG2Load log10(2) onto stack
FLDLN2Load ln(2) onto stack
FLDPILoad π onto stack
FLDZLoad 0.0 onto stack
FMULMultiply
FMULPMultiply and pop
FNCLEXClear exceptions, no wait
FNDISIDisable interrupts, no wait8087 only, otherwise FNOP
FNENIEnable interrupts, no wait8087 only, otherwise FNOP
FNINITInitialize floating point processor, no wait
FNOPNo operation
FNSAVESave FPU state, no wait, 8-bit
FNSAVEWSave FPU state, no wait, 16-bit
FNSTCWStore control word, no wait
FNSTENVStore FPU environment, no wait
FNSTENVWStore FPU environment, no wait, 16-bit
FNSTSWStore status word, no wait
FPATANPartial arctangent
FPREMPartial remainder
FPTANPartial tangent
FRNDINTRound to integer
FRSTORRestore saved state
FRSTORWRestore saved statePerhaps not actually available in 8087
FSAVESave FPU state
FSAVEWSave FPU state, 16-bit
FSCALEScale by factor of 2
FSQRTSquare root
FSTFloating point store
FSTCWStore control word
FSTENVStore FPU environment
FSTENVWStore FPU environment, 16-bit
FSTPStore and pop
FSTSWStore status word
FSUBSubtract
FSUBPSubtract and pop
FSUBRReverse subtract
FSUBRPReverse subtract and pop
FTSTTest for zero
FWAITWait while FPU is executing
FXAMExamine condition flags
FXCHExchange registers
FXTRACTExtract exponent and significand
FYL2Xy · log2 xif y = logb 2, then the base-b logarithm is computed
FYL2XP1y · log2 (x+1)more precise than log2 z if x is close to zero

Added with 80287
InstructionMeaningNotes
FSETPMSet protected mode80287 only, otherwise FNOP

Added with 80387
InstructionMeaningNotes
FCOSCosine
FLDENVDLoad environment state, 32-bit
FSAVEDSave FPU state, 32-bit
FPREM1Partial remainderComputes IEEE remainder
FRSTORDRestore saved state, 32-bit
FSINSine
FSINCOSSine and cosine
FSTENVDStore FPU environment, 32-bit
FUCOMUnordered compare
FUCOMPUnordered compare and pop
FUCOMPPUnordered compare and pop twice

Added with Pentium Pro
  • FCMOV variants: FCMOVB, FCMOVBE, FCMOVE, FCMOVNB, FCMOVNBE, FCMOVNE, FCMOVNU, FCMOVU
  • FCOMI variants: FCOMI, FCOMIP, FUCOMI, FUCOMIP

Added with SSE

FXRSTOR, FXSAVE

These are also supported on later Pentium IIs which do not contain SSE support

Added with SSE3

FISTTP (x87 to integer conversion with truncation regardless of status word)

SIMD instructions

MMX instructions

MMX instructions operate on the mm registers, which are 64 bits wide. They are shared with the FPU registers.

Original MMX instructions

Added with Pentium MMX

InstructionOpcodeMeaningNotes
EMMS0F 77Empty MMX Technology StateMarks all x87 FPU registers for use by FPU
MOVD mm, r/m320F 6E /rMove doubleword
MOVD r/m32, mm0F 7E /rMove doubleword
MOVQ mm/m64, mm0F 7F /rMove quadword
MOVQ mm, mm/m640F 6F /rMove quadword
MOVQ mm, r/m64REX.W + 0F 6E /rMove quadword
MOVQ r/m64, mmREX.W + 0F 7E /rMove quadword
PACKSSDW mm1, mm2/m640F 6B /rPack doublewords to words (signed with saturation)
PACKSSWB mm1, mm2/m640F 63 /rPack words to bytes (signed with saturation)
PACKUSWB mm, mm/m640F 67 /rPack words to bytes (unsigned with saturation)
PADDB mm, mm/m640F FC /rAdd packed byte integers
PADDW mm, mm/m640F FD /rAdd packed word integers
PADDD mm, mm/m640F FE /rAdd packed doubleword integers
PADDQ mm, mm/m640F D4 /rAdd packed quadword integers
PADDSB mm, mm/m640F EC /rAdd packed signed byte integers and saturate
PADDSW mm, mm/m640F ED /rAdd packed signed word integers and saturate
PADDUSB mm, mm/m640F DC /rAdd packed unsigned byte integers and saturate
PADDUSW mm, mm/m640F DD /rAdd packed unsigned word integers and saturate
PAND mm, mm/m640F DB /rBitwise AND
PANDN mm, mm/m640F DF /rBitwise AND NOT
POR mm, mm/m640F EB /rBitwise OR
PXOR mm, mm/m640F EF /rBitwise XOR
PCMPEQB mm, mm/m640F 74 /rCompare packed bytes for equality
PCMPEQW mm, mm/m640F 75 /rCompare packed words for equality
PCMPEQD mm, mm/m640F 76 /rCompare packed doublewords for equality
PCMPGTB mm, mm/m640F 64 /rCompare packed signed byte integers for greater than
PCMPGTW mm, mm/m640F 65 /rCompare packed signed word integers for greater than
PCMPGTD mm, mm/m640F 66 /rCompare packed signed doubleword integers for greater than
PMADDWD mm, mm/m640F F5 /rMultiply packed words, add adjacent doubleword results
PMULHW mm, mm/m640F E5 /rMultiply packed signed word integers, store high 16 bits of results
PMULLW mm, mm/m640F D5 /rMultiply packed signed word integers, store low 16 bits of results
PSLLW mm1, imm80F 71 /6 ibShift left words, shift in zeros
PSLLW mm, mm/m640F F1 /rShift left words, shift in zeros
PSLLD mm, imm80F 72 /6 ibShift left doublewords, shift in zeros
PSLLD mm, mm/m640F F2 /rShift left doublewords, shift in zeros
PSLLQ mm, imm80F 73 /6 ibShift left quadword, shift in zeros
PSLLQ mm, mm/m640F F3 /rShift left quadword, shift in zeros
PSRAD mm, imm80F 72 /4 ibShift right doublewords, shift in sign bits
PSRAD mm, mm/m640F E2 /rShift right doublewords, shift in sign bits
PSRAW mm, imm80F 71 /4 ibShift right words, shift in sign bits
PSRAW mm, mm/m640F E1 /rShift right words, shift in sign bits
PSRLW mm, imm80F 71 /2 ibShift right words, shift in zeros
PSRLW mm, mm/m640F D1 /rShift right words, shift in zeros
PSRLD mm, imm80F 72 /2 ibShift right doublewords, shift in zeros
PSRLD mm, mm/m640F D2 /rShift right doublewords, shift in zeros
PSRLQ mm, imm80F 73 /2 ibShift right quadword, shift in zeros
PSRLQ mm, mm/m640F D3 /rShift right quadword, shift in zeros
PSUBB mm, mm/m640F F8 /rSubtract packed byte integers
PSUBW mm, mm/m640F F9 /rSubtract packed word integers
PSUBD mm, mm/m640F FA /rSubtract packed doubleword integers
PSUBSB mm, mm/m640F E8 /rSubtract signed packed bytes with saturation
PSUBSW mm, mm/m640F E9 /rSubtract signed packed words with saturation
PSUBUSB mm, mm/m640F D8 /rSubtract unsigned packed bytes with saturation
PSUBUSW mm, mm/m640F D9 /rSubtract unsigned packed words with saturation
PUNPCKHBW mm, mm/m640F 68 /rUnpack and interleave high-order bytes
PUNPCKHWD mm, mm/m640F 69 /rUnpack and interleave high-order words
PUNPCKHDQ mm, mm/m640F 6A /rUnpack and interleave high-order doublewords
PUNPCKLBW mm, mm/m320F 60 /rUnpack and interleave low-order bytes
PUNPCKLWD mm, mm/m320F 61 /rUnpack and interleave low-order words
PUNPCKLDQ mm, mm/m320F 62 /rUnpack and interleave low-order doublewords
EMMI instructions

Added with 6x86MX from Cyrix, deprecated now

PAVEB, PADDSIW, PMAGW, PDISTIB, PSUBSIW, PMVZB, PMULHRW, PMVNZB, PMVLZB, PMVGEZB, PMULHRIW, PMACHRIW

MMX instructions added with MMX+ and SSE

The following MMX instruction were added with SSE. They are also available on the Athlon under the name MMX+.

InstructionOpcodeMeaning
MASKMOVQ mm1, mm20F F7 /rMasked Move of Quadword
MOVNTQ m64, mm0F E7 /rMove Quadword Using Non-Temporal Hint
PSHUFW mm1, mm2/m64, imm80F 70 /r ibShuffle Packed Words
PINSRW mm, r32/m16, imm80F C4 /rInsert Word
PEXTRW reg, mm, imm80F C5 /rExtract Word
PMOVMSKB reg, mm0F D7 /rMove Byte Mask
PMINUB mm1, mm2/m640F DA /rMinimum of Packed Unsigned Byte Integers
PMAXUB mm1, mm2/m640F DE /rMaximum of Packed Unsigned Byte Integers
PAVGB mm1, mm2/m640F E0 /rAverage Packed Integers
PAVGW mm1, mm2/m640F E3 /rAverage Packed Integers
PMULHUW mm1, mm2/m640F E4 /rMultiply Packed Unsigned Integers and Store High Result
PMINSW mm1, mm2/m640F EA /rMinimum of Packed Signed Word Integers
PMAXSW mm1, mm2/m640F EE /rMaximum of Packed Signed Word Integers
PSADBW mm1, mm2/m640F F6 /rCompute Sum of Absolute Differences
MMX instructions added with SSE2

The following MMX instructions were added with SSE2:

InstructionOpcodeMeaning
PSUBQ mm1, mm2/m640F FB /rSubtract quadword integer
PMULUDQ mm1, mm2/m640F F4 /rMultiply unsigned doubleword integer
MMX instructions added with SSSE3
InstructionOpcodeMeaning
PSIGNB mm1, mm2/m640F 38 08 /rNegate/zero/preserve packed byte integers depending on corresponding sign
PSIGNW mm1, mm2/m640F 38 09 /rNegate/zero/preserve packed word integers depending on corresponding sign
PSIGND mm1, mm2/m640F 38 0A /rNegate/zero/preserve packed doubleword integers depending on corresponding sign
PSHUFB mm1, mm2/m640F 38 00 /rShuffle bytes
PMULHRSW mm1, mm2/m640F 38 0B /rMultiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits
PMADDUBSW mm1, mm2/m640F 38 04 /rMultiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words
PHSUBW mm1, mm2/m640F 38 05 /rSubtract and pack 16-bit signed integers horizontally
PHSUBSW mm1, mm2/m640F 38 07 /rSubtract and pack 16-bit signed integer horizontally with saturation
PHSUBD mm1, mm2/m640F 38 06 /rSubtract and pack 32-bit signed integers horizontally
PHADDSW mm1, mm2/m640F 38 03 /rAdd and pack 16-bit signed integers horizontally, pack saturated integers to mm1.
PHADDW mm1, mm2/m640F 38 01 /rAdd and pack 16-bit integers horizontally
PHADDD mm1, mm2/m640F 38 02 /rAdd and pack 32-bit integers horizontally
PALIGNR mm1, mm2/m64, imm80F 3A 0F /r ibConcatenate destination and source operands, extract byte-aligned result shifted to the right
PABSB mm1, mm2/m640F 38 1C /rCompute the absolute value of bytes and store unsigned result
PABSW mm1, mm2/m640F 38 1D /rCompute the absolute value of 16-bit integers and store unsigned result
PABSD mm1, mm2/m640F 38 1E /rCompute the absolute value of 32-bit integers and store unsigned result

3DNow! instructions

Added with K6-2

FEMMS, PAVGUSB, PF2ID, PFACC, PFADD, PFCMPEQ, PFCMPGE, PFCMPGT, PFMAX, PFMIN, PFMUL, PFRCP, PFRCPIT1, PFRCPIT2, PFRSQIT1, PFRSQRT, PFSUB, PFSUBR, PI2FD, PMULHRW, PREFETCH, PREFETCHW

Added with Athlon and K6-2+

PF2IW, PFNACC, PFPNACC, PI2FW, PSWAPD

Added with Geode GX

PFRSQRTV, PFRCPV

SSE instructions

Added with Pentium III

SSE instructions operate on xmm registers, which are 128 bit wide.

SSE consists of the following SSE SIMD floating-point instructions:

InstructionOpcodeMeaning
ANDPS* xmm1, xmm2/m1280F 54 /rBitwise Logical AND of Packed Single-Precision Floating-Point Values
ANDNPS* xmm1, xmm2/m1280F 55 /rBitwise Logical AND NOT of Packed Single-Precision Floating-Point Values
ORPS* xmm1, xmm2/m1280F 56 /rBitwise Logical OR of Single-Precision Floating-Point Values
XORPS* xmm1, xmm2/m1280F 57 /rBitwise Logical XOR for Single-Precision Floating-Point Values
MOVUPS xmm1, xmm2/m1280F 10 /rMove Unaligned Packed Single-Precision Floating-Point Values
MOVSS xmm1, xmm2/m32F3 0F 10 /rMove Scalar Single-Precision Floating-Point Values
MOVUPS xmm2/m128, xmm10F 11 /rMove Unaligned Packed Single-Precision Floating-Point Values
MOVSS xmm2/m32, xmm1F3 0F 11 /rMove Scalar Single-Precision Floating-Point Values
MOVLPS xmm, m640F 12 /rMove Low Packed Single-Precision Floating-Point Values
MOVHLPS xmm1, xmm20F 12 /rMove Packed Single-Precision Floating-Point Values High to Low
MOVLPS m64, xmm0F 13 /rMove Low Packed Single-Precision Floating-Point Values
UNPCKLPS xmm1, xmm2/m1280F 14 /rUnpack and Interleave Low Packed Single-Precision Floating-Point Values
UNPCKHPS xmm1, xmm2/m1280F 15 /rUnpack and Interleave High Packed Single-Precision Floating-Point Values
MOVHPS xmm, m640F 16 /rMove High Packed Single-Precision Floating-Point Values
MOVLHPS xmm1, xmm20F 16 /rMove Packed Single-Precision Floating-Point Values Low to High
MOVHPS m64, xmm0F 17 /rMove High Packed Single-Precision Floating-Point Values
MOVAPS xmm1, xmm2/m1280F 28 /rMove Aligned Packed Single-Precision Floating-Point Values
MOVAPS xmm2/m128, xmm10F 29 /rMove Aligned Packed Single-Precision Floating-Point Values
MOVNTPS m128, xmm10F 2B /rMove Aligned Four Packed Single-FP Non Temporal
MOVMSKPS reg, xmm0F 50 /rExtract Packed Single-Precision Floating-Point 4-bit Sign Mask. The upper bits of the register are filled with zeros.
CVTPI2PS xmm, mm/m640F 2A /rConvert Packed Dword Integers to Packed Single-Precision FP Values
CVTSI2SS xmm, r/m32F3 0F 2A /rConvert Dword Integer to Scalar Single-Precision FP Value
CVTSI2SS xmm, r/m64F3 REX.W 0F 2A /rConvert Qword Integer to Scalar Single-Precision FP Value
MOVNTPS m128, xmm0F 2B /rStore Packed Single-Precision Floating-Point Values Using Non-Temporal Hint
CVTTPS2PI mm, xmm/m640F 2C /rConvert with Truncation Packed Single-Precision FP Values to Packed Dword Integers
CVTTSS2SI r32, xmm/m32F3 0F 2C /rConvert with Truncation Scalar Single-Precision FP Value to Dword Integer
CVTTSS2SI r64, xmm1/m32F3 REX.W 0F 2C /rConvert with Truncation Scalar Single-Precision FP Value to Qword Integer
CVTPS2PI mm, xmm/m640F 2D /rConvert Packed Single-Precision FP Values to Packed Dword Integers
CVTSS2SI r32, xmm/m32F3 0F 2D /rConvert Scalar Single-Precision FP Value to Dword Integer
CVTSS2SI r64, xmm1/m32F3 REX.W 0F 2D /rConvert Scalar Single-Precision FP Value to Qword Integer
UCOMISS xmm1, xmm2/m320F 2E /rUnordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS
COMISS xmm1, xmm2/m320F 2F /rCompare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS
SQRTPS xmm1, xmm2/m1280F 51 /rCompute Square Roots of Packed Single-Precision Floating-Point Values
SQRTSS xmm1, xmm2/m32F3 0F 51 /rCompute Square Root of Scalar Single-Precision Floating-Point Value
RSQRTPS xmm1, xmm2/m1280F 52 /rCompute Reciprocal of Square Root of Packed Single-Precision Floating-Point Value
RSQRTSS xmm1, xmm2/m32F3 0F 52 /rCompute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value
RCPPS xmm1, xmm2/m1280F 53 /rCompute Reciprocal of Packed Single-Precision Floating-Point Values
RCPSS xmm1, xmm2/m32F3 0F 53 /rCompute Reciprocal of Scalar Single-Precision Floating-Point Values
ADDPS xmm1, xmm2/m1280F 58 /rAdd Packed Single-Precision Floating-Point Values
ADDSS xmm1, xmm2/m32F3 0F 58 /rAdd Scalar Single-Precision Floating-Point Values
MULPS xmm1, xmm2/m1280F 59 /rMultiply Packed Single-Precision Floating-Point Values
MULSS xmm1, xmm2/m32F3 0F 59 /rMultiply Scalar Single-Precision Floating-Point Values
SUBPS xmm1, xmm2/m1280F 5C /rSubtract Packed Single-Precision Floating-Point Values
SUBSS xmm1, xmm2/m32F3 0F 5C /rSubtract Scalar Single-Precision Floating-Point Values
MINPS xmm1, xmm2/m1280F 5D /rReturn Minimum Packed Single-Precision Floating-Point Values
MINSS xmm1, xmm2/m32F3 0F 5D /rReturn Minimum Scalar Single-Precision Floating-Point Values
DIVPS xmm1, xmm2/m1280F 5E /rDivide Packed Single-Precision Floating-Point Values
DIVSS xmm1, xmm2/m32F3 0F 5E /rDivide Scalar Single-Precision Floating-Point Values
MAXPS xmm1, xmm2/m1280F 5F /rReturn Maximum Packed Single-Precision Floating-Point Values
MAXSS xmm1, xmm2/m32F3 0F 5F /rReturn Maximum Scalar Single-Precision Floating-Point Values
LDMXCSR m320F AE /2Load MXCSR Register State
STMXCSR m320F AE /3Store MXCSR Register State
CMPPS xmm1, xmm2/m128, imm80F C2 /r ibCompare Packed Single-Precision Floating-Point Values
CMPSS xmm1, xmm2/m32, imm8F3 0F C2 /r ibCompare Scalar Single-Precision Floating-Point Values
SHUFPS xmm1, xmm2/m128, imm80F C6 /r ibShuffle Packed Single-Precision Floating-Point Values
  • The floating point single bitwise operations ANDPS, ANDNPS, ORPS and XORPS produce the same result as the SSE2 integer (PAND, PANDN, POR, PXOR) and double ones (ANDPD, ANDNPD, ORPD, XORPD), but can introduce extra latency for domain changes when applied values of the wrong type.[11]

SSE2 instructions

Added with Pentium 4

SSE2 data movement instructions
InstructionOpcodeMeaning
MOVAPD xmm1, xmm2/m12866 0F 28 /rMove Aligned Packed Double-Precision Floating-Point Values
MOVAPD xmm2/m128, xmm166 0F 29 /rMove Aligned Packed Double-Precision Floating-Point Values
MOVNTPD m128, xmm166 0F 2B /rStore Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
MOVHPD xmm1, m6466 0F 16 /rMove High Packed Double-Precision Floating-Point Value
MOVHPD m64, xmm166 0F 17 /rMove High Packed Double-Precision Floating-Point Value
MOVLPD xmm1, m6466 0F 12 /rMove Low Packed Double-Precision Floating-Point Value
MOVLPD m64, xmm166 0F 13/rMove Low Packed Double-Precision Floating-Point Value
MOVUPD xmm1, xmm2/m12866 0F 10 /rMove Unaligned Packed Double-Precision Floating-Point Values
MOVUPD xmm2/m128, xmm166 0F 11 /rMove Unaligned Packed Double-Precision Floating-Point Values
MOVMSKPD reg, xmm66 0F 50 /rExtract Packed Double-Precision Floating-Point Sign Mask
MOVSD* xmm1, xmm2/m64F2 0F 10 /rMove or Merge Scalar Double-Precision Floating-Point Value
MOVSD xmm1/m64, xmm2F2 0F 11 /rMove or Merge Scalar Double-Precision Floating-Point Value
SSE2 packed arithmetic instructions
InstructionOpcodeMeaning
ADDPD xmm1, xmm2/m12866 0F 58 /rAdd Packed Double-Precision Floating-Point Values
ADDSD xmm1, xmm2/m64F2 0F 58 /rAdd Low Double-Precision Floating-Point Value
DIVPD xmm1, xmm2/m12866 0F 5E /rDivide Packed Double-Precision Floating-Point Values
DIVSD xmm1, xmm2/m64F2 0F 5E /rDivide Scalar Double-Precision Floating-Point Value
MAXPD xmm1, xmm2/m12866 0F 5F /rMaximum of Packed Double-Precision Floating-Point Values
MAXSD xmm1, xmm2/m64F2 0F 5F /rReturn Maximum Scalar Double-Precision Floating-Point Value
MINPD xmm1, xmm2/m12866 0F 5D /rMinimum of Packed Double-Precision Floating-Point Values
MINSD xmm1, xmm2/m64F2 0F 5D /rReturn Minimum Scalar Double-Precision Floating-Point Value
MULPD xmm1, xmm2/m12866 0F 59 /rMultiply Packed Double-Precision Floating-Point Values
MULSD xmm1,xmm2/m64F2 0F 59 /rMultiply Scalar Double-Precision Floating-Point Value
SQRTPD xmm1, xmm2/m12866 0F 51 /rSquare Root of Double-Precision Floating-Point Values
SQRTSD xmm1,xmm2/m64F2 0F 51/rCompute Square Root of Scalar Double-Precision Floating-Point Value
SUBPD xmm1, xmm2/m12866 0F 5C /rSubtract Packed Double-Precision Floating-Point Values
SUBSD xmm1, xmm2/m64F2 0F 5C /rSubtract Scalar Double-Precision Floating-Point Value
SSE2 logical instructions
InstructionOpcodeMeaning
ANDPD xmm1, xmm2/m12866 0F 54 /rBitwise Logical AND of Packed Double Precision Floating-Point Values
ANDNPD xmm1, xmm2/m12866 0F 55 /rBitwise Logical AND NOT of Packed Double Precision Floating-Point Values
ORPD xmm1, xmm2/m12866 0F 56/rBitwise Logical OR of Packed Double Precision Floating-Point Values
XORPD xmm1, xmm2/m12866 0F 57/rBitwise Logical XOR of Packed Double Precision Floating-Point Values
SSE2 compare instructions
InstructionOpcodeMeaning
CMPPD xmm1, xmm2/m128, imm866 0F C2 /r ibCompare Packed Double-Precision Floating-Point Values
CMPSD* xmm1, xmm2/m64, imm8F2 0F C2 /r ibCompare Low Double-Precision Floating-Point Values
COMISD xmm1, xmm2/m6466 0F 2F /rCompare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
UCOMISD xmm1, xmm2/m6466 0F 2E /rUnordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS
SSE2 shuffle and unpack instructions
InstructionOpcodeMeaning
SHUFPD xmm1, xmm2/m128, imm866 0F C6 /r ibPacked Interleave Shuffle of Pairs of Double-Precision Floating-Point Values
UNPCKHPD xmm1, xmm2/m12866 0F 15 /rUnpack and Interleave High Packed Double-Precision Floating-Point Values
UNPCKLPD xmm1, xmm2/m12866 0F 14 /rUnpack and Interleave Low Packed Double-Precision Floating-Point Values
SSE2 conversion instructions
InstructionOpcodeMeaning
CVTDQ2PD xmm1, xmm2/m64F3 0F E6 /rConvert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
CVTDQ2PS xmm1, xmm2/m1280F 5B /rConvert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
CVTPD2DQ xmm1, xmm2/m128F2 0F E6 /rConvert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
CVTPD2PI mm, xmm/m12866 0F 2D /rConvert Packed Double-Precision FP Values to Packed Dword Integers
CVTPD2PS xmm1, xmm2/m12866 0F 5A /rConvert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
CVTPI2PD xmm, mm/m6466 0F 2A /rConvert Packed Dword Integers to Packed Double-Precision FP Values
CVTPS2DQ xmm1, xmm2/m12866 0F 5B /rConvert Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values
CVTPS2PD xmm1, xmm2/m640F 5A /rConvert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
CVTSD2SI r32, xmm1/m64F2 0F 2D /rConvert Scalar Double-Precision Floating-Point Value to Doubleword Integer
CVTSD2SI r64, xmm1/m64F2 REX.W 0F 2D /rConvert Scalar Double-Precision Floating-Point Value to Quadword Integer With Sign Extension
CVTSD2SS xmm1, xmm2/m64F2 0F 5A /rConvert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
CVTSI2SD xmm1, r32/m32F2 0F 2A /rConvert Doubleword Integer to Scalar Double-Precision Floating-Point Value
CVTSI2SD xmm1, r/m64F2 REX.W 0F 2A /rConvert Quadword Integer to Scalar Double-Precision Floating-Point value
CVTSS2SD xmm1, xmm2/m32F3 0F 5A /rConvert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
CVTTPD2DQ xmm1, xmm2/m12866 0F E6 /rConvert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
CVTTPD2PI mm, xmm/m12866 0F 2C /rConvert with Truncation Packed Double-Precision FP Values to Packed Dword Integers
CVTTPS2DQ xmm1, xmm2/m128F3 0F 5B /rConvert with Truncation Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values
CVTTSD2SI r32, xmm1/m64F2 0F 2C /rConvert with Truncation Scalar Double-Precision Floating-Point Value to Signed Dword Integer
CVTTSD2SI r64, xmm1/m64F2 REX.W 0F 2C /rConvert with Truncation Scalar Double-Precision Floating-Point Value To Signed Qword Integer
SSE2 MMX-like instructions extended to SSE registers

SSE2 allows execution of MMX instructions on SSE registers, processing twice the amount of data at once.

InstructionOpcodeMeaning
MOVD xmm, r/m3266 0F 6E /rMove doubleword
MOVD r/m32, xmm66 0F 7E /rMove doubleword
MOVQ xmm1, xmm2/m64F3 0F 7E /rMove quadword
MOVQ xmm2/m64, xmm166 0F D6 /rMove quadword
MOVQ r/m64, xmm66 REX.W 0F 7E /rMove quadword
MOVQ xmm, r/m6466 REX.W 0F 6E /rMove quadword
PMOVMSKB reg, xmm66 0F D7 /rMove a byte mask, zeroing the upper bits of the register
PEXTRW reg, xmm, imm866 0F C5 /r ibExtract specified word and move it to reg, setting bits 15-0 and zeroing the rest
PINSRW xmm, r32/m16, imm866 0F C4 /r ibMove low word at the specified word position
PACKSSDW xmm1, xmm2/m12866 0F 6B /rConverts 4 packed signed doubleword integers into 8 packed signed word integers with saturation
PACKSSWB xmm1, xmm2/m12866 0F 63 /rConverts 8 packed signed word integers into 16 packed signed byte integers with saturation
PACKUSWB xmm1, xmm2/m12866 0F 67 /rConverts 8 signed word integers into 16 unsigned byte integers with saturation
PADDB xmm1, xmm2/m12866 0F FC /rAdd packed byte integers
PADDW xmm1, xmm2/m12866 0F FD /rAdd packed word integers
PADDD xmm1, xmm2/m12866 0F FE /rAdd packed doubleword integers
PADDQ xmm1, xmm2/m12866 0F D4 /rAdd packed quadword integers.
PADDSB xmm1, xmm2/m12866 0F EC /rAdd packed signed byte integers with saturation
PADDSW xmm1, xmm2/m12866 0F ED /rAdd packed signed word integers with saturation
PADDUSB xmm1, xmm2/m12866 0F DC /rAdd packed unsigned byte integers with saturation
PADDUSW xmm1, xmm2/m12866 0F DD /rAdd packed unsigned word integers with saturation
PAND xmm1, xmm2/m12866 0F DB /rBitwise AND
PANDN xmm1, xmm2/m12866 0F DF /rBitwise AND NOT
POR xmm1, xmm2/m12866 0F EB /rBitwise OR
PXOR xmm1, xmm2/m12866 0F EF /rBitwise XOR
PCMPEQB xmm1, xmm2/m12866 0F 74 /rCompare packed bytes for equality.
PCMPEQW xmm1, xmm2/m12866 0F 75 /rCompare packed words for equality.
PCMPEQD xmm1, xmm2/m12866 0F 76 /rCompare packed doublewords for equality.
PCMPGTB xmm1, xmm2/m12866 0F 64 /rCompare packed signed byte integers for greater than
PCMPGTW xmm1, xmm2/m12866 0F 65 /rCompare packed signed word integers for greater than
PCMPGTD xmm1, xmm2/m12866 0F 66 /rCompare packed signed doubleword integers for greater than
PMULLW xmm1, xmm2/m12866 0F D5 /rMultiply packed signed word integers with saturation
PMULHW xmm1, xmm2/m12866 0F E5 /rMultiply the packed signed word integers, store the high 16 bits of the results
PMULHUW xmm1, xmm2/m12866 0F E4 /rMultiply packed unsigned word integers, store the high 16 bits of the results
PMULUDQ xmm1, xmm2/m12866 0F F4 /rMultiply packed unsigned doubleword integers
PSLLW xmm1, xmm2/m12866 0F F1 /rShift words left while shifting in 0s
PSLLW xmm1, imm866 0F 71 /6 ibShift words left while shifting in 0s
PSLLD xmm1, xmm2/m12866 0F F2 /rShift doublewords left while shifting in 0s
PSLLD xmm1, imm866 0F 72 /6 ibShift doublewords left while shifting in 0s
PSLLQ xmm1, xmm2/m12866 0F F3 /rShift quadwords left while shifting in 0s
PSLLQ xmm1, imm866 0F 73 /6 ibShift quadwords left while shifting in 0s
PSRAD xmm1, xmm2/m12866 0F E2 /rShift doubleword right while shifting in sign bits
PSRAD xmm1, imm866 0F 72 /4 ibShift doublewords right while shifting in sign bits
PSRAW xmm1, xmm2/m12866 0F E1 /rShift words right while shifting in sign bits
PSRAW xmm1, imm866 0F 71 /4 ibShift words right while shifting in sign bits
PSRLW xmm1, xmm2/m12866 0F D1 /rShift words right while shifting in 0s
PSRLW xmm1, imm866 0F 71 /2 ibShift words right while shifting in 0s
PSRLD xmm1, xmm2/m12866 0F D2 /rShift doublewords right while shifting in 0s
PSRLD xmm1, imm866 0F 72 /2 ibShift doublewords right while shifting in 0s
PSRLQ xmm1, xmm2/m12866 0F D3 /rShift quadwords right while shifting in 0s
PSRLQ xmm1, imm866 0F 73 /2 ibShift quadwords right while shifting in 0s
PSUBB xmm1, xmm2/m12866 0F F8 /rSubtract packed byte integers
PSUBW xmm1, xmm2/m12866 0F F9 /rSubtract packed word integers
PSUBD xmm1, xmm2/m12866 0F FA /rSubtract packed doubleword integers
PSUBQ xmm1, xmm2/m12866 0F FB /rSubtract packed quadword integers.
PSUBSB xmm1, xmm2/m12866 0F E8 /rSubtract packed signed byte integers with saturation
PSUBSW xmm1, xmm2/m12866 0F E9 /rSubtract packed signed word integers with saturation
PMADDWD xmm1, xmm2/m12866 0F F5 /rMultiply the packed word integers, add adjacent doubleword results
PSUBUSB xmm1, xmm2/m12866 0F D8 /rSubtract packed unsigned byte integers with saturation
PSUBUSW xmm1, xmm2/m12866 0F D9 /rSubtract packed unsigned word integers with saturation
PUNPCKHBW xmm1, xmm2/m12866 0F 68 /rUnpack and interleave high-order bytes
PUNPCKHWD xmm1, xmm2/m12866 0F 69 /rUnpack and interleave high-order words
PUNPCKHDQ xmm1, xmm2/m12866 0F 6A /rUnpack and interleave high-order doublewords
PUNPCKLBW xmm1, xmm2/m12866 0F 60 /rInterleave low-order bytes
PUNPCKLWD xmm1, xmm2/m12866 0F 61 /rInterleave low-order words
PUNPCKLDQ xmm1, xmm2/m12866 0F 62 /rInterleave low-order doublewords
PAVGB xmm1, xmm2/m12866 0F E0, /rAverage packed unsigned byte integers with rounding
PAVGW xmm1, xmm2/m12866 0F E3 /rAverage packed unsigned word integers with rounding
PMINUB xmm1, xmm2/m12866 0F DA /rCompare packed unsigned byte integers and store packed minimum values
PMINSW xmm1, xmm2/m12866 0F EA /rCompare packed signed word integers and store packed minimum values
PMAXSW xmm1, xmm2/m12866 0F EE /rCompare packed signed word integers and store maximum packed values
PMAXUB xmm1, xmm2/m12866 0F DE /rCompare packed unsigned byte integers and store packed maximum values
PSADBW xmm1, xmm2/m12866 0F F6 /rComputes the absolute differences of the packed unsigned byte integers; the 8 low differences and 8 high differences are then summed separately to produce two unsigned word integer results
SSE2 integer instructions for SSE registers only

The following instructions can be used only on SSE registers, since by their nature they do not work on MMX registers

InstructionOpcodeMeaning
MASKMOVDQU xmm1, xmm266 0F F7 /rNon-Temporal Store of Selected Bytes from an XMM Register into Memory
MOVDQ2Q mm, xmmF2 0F D6 /rMove low quadword from XMM to MMX register.
MOVDQA xmm1, xmm2/m12866 0F 6F /rMove aligned double quadword
MOVDQA xmm2/m128, xmm166 0F 7F /rMove aligned double quadword
MOVDQU xmm1, xmm2/m128F3 0F 6F /rMove unaligned double quadword
MOVDQU xmm2/m128, xmm1F3 0F 7F /rMove unaligned double quadword
MOVQ2DQ xmm, mmF3 0F D6 /rMove quadword from MMX register to low quadword of XMM register
MOVNTDQ m128, xmm166 0F E7 /rStore Packed Integers Using Non-Temporal Hint
PSHUFHW xmm1, xmm2/m128, imm8F3 0F 70 /r ibShuffle packed high words.
PSHUFLW xmm1, xmm2/m128, imm8F2 0F 70 /r ibShuffle packed low words.
PSHUFD xmm1, xmm2/m128, imm866 0F 70 /r ibShuffle packed doublewords.
PSLLDQ xmm1, imm866 0F 73 /7 ibPacked shift left logical double quadwords.
PSRLDQ xmm1, imm866 0F 73 /3 ibPacked shift right logical double quadwords.
PUNPCKHQDQ xmm1, xmm2/m12866 0F 6D /rUnpack and interleave high-order quadwords,
PUNPCKLQDQ xmm1, xmm2/m12866 0F 6C /rInterleave low quadwords,

SSE3 instructions

Added with Pentium 4 supporting SSE3

SSE3 SIMD floating-point instructions
InstructionOpcodeMeaningNotes
ADDSUBPS xmm1, xmm2/m128F2 0F D0 /rAdd/subtract single-precision floating-point valuesfor Complex Arithmetic
ADDSUBPD xmm1, xmm2/m12866 0F D0 /rAdd/subtract double-precision floating-point values
MOVDDUP xmm1, xmm2/m64F2 0F 12 /rMove double-precision floating-point value and duplicate
MOVSLDUP xmm1, xmm2/m128F3 0F 12 /rMove and duplicate even index single-precision floating-point values
MOVSHDUP xmm1, xmm2/m128F3 0F 16 /rMove and duplicate odd index single-precision floating-point values
HADDPS xmm1, xmm2/m128F2 0F 7C /rHorizontal add packed single-precision floating-point valuesfor Graphics
HADDPD xmm1, xmm2/m12866 0F 7C /rHorizontal add packed double-precision floating-point values
HSUBPS xmm1, xmm2/m128F2 0F 7D /rHorizontal subtract packed single-precision floating-point values
HSUBPD xmm1, xmm2/m12866 0F 7D /rHorizontal subtract packed double-precision floating-point values

SSE3 SIMD integer instructions
InstructionOpcodeMeaningNotes
LDDQU xmm1, memF2 0F F0 /rLoad unaligned data and return double quadwordInstructionally equivalent to MOVDQU. For video encoding

SSSE3 instructions

Added with Xeon 5100 series and initial Core 2

The following MMX-like instructions extended to SSE registers were added with SSSE3

InstructionOpcodeMeaning
PSIGNB xmm1, xmm2/m12866 0F 38 08 /rNegate/zero/preserve packed byte integers depending on corresponding sign
PSIGNW xmm1, xmm2/m12866 0F 38 09 /rNegate/zero/preserve packed word integers depending on corresponding sign
PSIGND xmm1, xmm2/m12866 0F 38 0A /rNegate/zero/preserve packed doubleword integers depending on corresponding
PSHUFB xmm1, xmm2/m12866 0F 38 00 /rShuffle bytes
PMULHRSW xmm1, xmm2/m12866 0F 38 0B /rMultiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits
PMADDUBSW xmm1, xmm2/m12866 0F 38 04 /rMultiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words
PHSUBW xmm1, xmm2/m12866 0F 38 05 /rSubtract and pack 16-bit signed integers horizontally
PHSUBSW xmm1, xmm2/m12866 0F 38 07 /rSubtract and pack 16-bit signed integer horizontally with saturation
PHSUBD xmm1, xmm2/m12866 0F 38 06 /rSubtract and pack 32-bit signed integers horizontally
PHADDSW xmm1, xmm2/m12866 0F 38 03 /rAdd and pack 16-bit signed integers horizontally with saturation
PHADDW xmm1, xmm2/m12866 0F 38 01 /rAdd and pack 16-bit integers horizontally
PHADDD xmm1, xmm2/m12866 0F 38 02 /rAdd and pack 32-bit integers horizontally
PALIGNR xmm1, xmm2/m128, imm866 0F 3A 0F /r ibConcatenate destination and source operands, extract byte-aligned result shifted to the right
PABSB xmm1, xmm2/m12866 0F 38 1C /rCompute the absolute value of bytes and store unsigned result
PABSW xmm1, xmm2/m12866 0F 38 1D /rCompute the absolute value of 16-bit integers and store unsigned result
PABSD xmm1, xmm2/m12866 0F 38 1E /rCompute the absolute value of 32-bit integers and store unsigned result

SSE4.1

Added with Core 2 manufactured in 45nm

SSE4.1 SIMD floating-point instructions
InstructionOpcodeMeaning
DPPS xmm1, xmm2/m128, imm866 0F 3A 40 /r ibSelectively multiply packed SP floating-point values, add and selectively store
DPPD xmm1, xmm2/m128, imm866 0F 3A 41 /r ibSelectively multiply packed DP floating-point values, add and selectively store
BLENDPS xmm1, xmm2/m128, imm866 0F 3A 0C /r ibSelect packed single precision floating-point values from specified mask
BLENDVPS xmm1, xmm2/m128, <XMM0>66 0F 38 14 /rSelect packed single precision floating-point values from specified mask
BLENDPD xmm1, xmm2/m128, imm866 0F 3A 0D /r ibSelect packed DP-FP values from specified mask
BLENDVPD xmm1, xmm2/m128 , <XMM0>66 0F 38 15 /rSelect packed DP FP values from specified mask
ROUNDPS xmm1, xmm2/m128, imm866 0F 3A 08 /r ibRound packed single precision floating-point values
ROUNDSS xmm1, xmm2/m32, imm866 0F 3A 0A /r ibRound the low packed single precision floating-point value
ROUNDPD xmm1, xmm2/m128, imm866 0F 3A 09 /r ibRound packed double precision floating-point values
ROUNDSD xmm1, xmm2/m64, imm866 0F 3A 0B /r ibRound the low packed double precision floating-point value
INSERTPS xmm1, xmm2/m32, imm866 0F 3A 21 /r ibInsert a selected single-precision floating-point value at the specified destination element and zero out destination elements
EXTRACTPS reg/m32, xmm1, imm866 0F 3A 17 /r ibExtract one single-precision floating-point value at specified offset and store the result (zero-extended, if applicable)
SSE4.1 SIMD integer instructions
InstructionOpcodeMeaning
MPSADBW xmm1, xmm2/m128, imm866 0F 3A 42 /r ibSums absolute 8-bit integer difference of adjacent groups of 4 byte integers with starting offset
PHMINPOSUW xmm1, xmm2/m12866 0F 38 41 /rFind the minimum unsigned word
PMULLD xmm1, xmm2/m12866 0F 38 40 /rMultiply the packed dword signed integers and store the low 32 bits
PMULDQ xmm1, xmm2/m12866 0F 38 28 /rMultiply packed signed doubleword integers and store quadword result
PBLENDVB xmm1, xmm2/m128, <XMM0>66 0F 38 10 /rSelect byte values from specified mask
PBLENDW xmm1, xmm2/m128, imm866 0F 3A 0E /r ibSelect words from specified mask
PMINSB xmm1, xmm2/m12866 0F 38 38 /rCompare packed signed byte integers
PMINUW xmm1, xmm2/m12866 0F 38 3A/rCompare packed unsigned word integers
PMINSD xmm1, xmm2/m12866 0F 38 39 /rCompare packed signed dword integers
PMINUD xmm1, xmm2/m12866 0F 38 3B /rCompare packed unsigned dword integers
PMAXSB xmm1, xmm2/m12866 0F 38 3C /rCompare packed signed byte integers
PMAXUW xmm1, xmm2/m12866 0F 38 3E/rCompare packed unsigned word integers
PMAXSD xmm1, xmm2/m12866 0F 38 3D /rCompare packed signed dword integers
PMAXUD xmm1, xmm2/m12866 0F 38 3F /rCompare packed unsigned dword integers
PINSRB xmm1, r32/m8, imm866 0F 3A 20 /r ibInsert a byte integer value at specified destination element
PINSRD xmm1, r/m32, imm866 0F 3A 22 /r ibInsert a dword integer value at specified destination element
PINSRQ xmm1, r/m64, imm866 REX.W 0F 3A 22 /r ibInsert a qword integer value at specified destination element
PEXTRB reg/m8, xmm2, imm866 0F 3A 14 /r ibExtract a byte integer value at source byte offset, upper bits are zeroed.
PEXTRW reg/m16, xmm, imm866 0F 3A 15 /r ibExtract word and copy to lowest 16 bits, zero-extended
PEXTRD r/m32, xmm2, imm866 0F 3A 16 /r ibExtract a dword integer value at source dword offset
PEXTRQ r/m64, xmm2, imm866 REX.W 0F 3A 16 /r ibExtract a qword integer value at source qword offset
PMOVSXBW xmm1, xmm2/m6466 0f 38 20 /rSign extend 8 packed 8-bit integers to 8 packed 16-bit integers
PMOVZXBW xmm1, xmm2/m6466 0f 38 30 /rZero extend 8 packed 8-bit integers to 8 packed 16-bit integers
PMOVSXBD xmm1, xmm2/m3266 0f 38 21 /rSign extend 4 packed 8-bit integers to 4 packed 32-bit integers
PMOVZXBD xmm1, xmm2/m3266 0f 38 31 /rZero extend 4 packed 8-bit integers to 4 packed 32-bit integers
PMOVSXBQ xmm1, xmm2/m1666 0f 38 22 /rSign extend 2 packed 8-bit integers to 2 packed 64-bit integers
PMOVZXBQ xmm1, xmm2/m1666 0f 38 32 /rZero extend 2 packed 8-bit integers to 2 packed 64-bit integers
PMOVSXWD xmm1, xmm2/m6466 0f 38 23/rSign extend 4 packed 16-bit integers to 4 packed 32-bit integers
PMOVZXWD xmm1, xmm2/m6466 0f 38 33 /rZero extend 4 packed 16-bit integers to 4 packed 32-bit integers
PMOVSXWQ xmm1, xmm2/m3266 0f 38 24 /rSign extend 2 packed 16-bit integers to 2 packed 64-bit integers
PMOVZXWQ xmm1, xmm2/m3266 0f 38 34 /rZero extend 2 packed 16-bit integers to 2 packed 64-bit integers
PMOVSXDQ xmm1, xmm2/m6466 0f 38 25 /rSign extend 2 packed 32-bit integers to 2 packed 64-bit integers
PMOVZXDQ xmm1, xmm2/m6466 0f 38 35 /rZero extend 2 packed 32-bit integers to 2 packed 64-bit integers
PTEST xmm1, xmm2/m12866 0F 38 17 /rSet ZF if AND result is all 0s, set CF if AND NOT result is all 0s
PCMPEQQ xmm1, xmm2/m12866 0F 38 29 /rCompare packed qwords for equality
PACKUSDW xmm1, xmm2/m12866 0F 38 2B /rConvert 2 × 4 packed signed doubleword integers into 8 packed unsigned word integers with saturation
MOVNTDQA xmm1, m12866 0F 38 2A /rMove double quadword using non-temporal hint if WC memory type

SSE4a

Added with Phenom processors

  • EXTRQ/INSERTQ
  • MOVNTSD/MOVNTSS

SSE4.2

Added with Nehalem processors

InstructionOpcodeMeaning
PCMPESTRI xmm1, xmm2/m128, imm866 0F 3A 61 /r imm8Packed comparison of string data with explicit lengths, generating an index
PCMPESTRM xmm1, xmm2/m128, imm866 0F 3A 60 /r imm8Packed comparison of string data with explicit lengths, generating a mask
PCMPISTRI xmm1, xmm2/m128, imm866 0F 3A 63 /r imm8Packed comparison of string data with implicit lengths, generating an index
PCMPISTRM xmm1, xmm2/m128, imm866 0F 3A 62 /r imm8Packed comparison of string data with implicit lengths, generating a mask
PCMPGTQ xmm1,xmm2/m12866 0F 38 37 /rCompare packed signed qwords for greater than.

SSE5 derived instructions

SSE5 was a proposed SSE extension by AMD. The bundle did not include the full set of Intel's SSE4 instructions, making it a competitor to SSE4 rather than a successor. AMD chose not to implement SSE5 as originally proposed, however, derived SSE extensions were introduced.

XOP

Introduced with the bulldozer processor core, removed again from Zen (microarchitecture) onward.

A revision of most of the SSE5 instruction set

F16C

Half-precision floating-point conversion.

InstructionMeaning
VCVTPH2PS xmmreg,xmmrm64Convert four half-precision floating point values in memory or the bottom half of an XMM register to four single-precision floating-point values in an XMM register
VCVTPH2PS ymmreg,xmmrm128Convert eight half-precision floating point values in memory or an XMM register (the bottom half of a YMM register) to eight single-precision floating-point values in a YMM register
VCVTPS2PH xmmrm64,xmmreg,imm8Convert four single-precision floating point values in an XMM register to half-precision floating-point values in memory or the bottom half an XMM register
VCVTPS2PH xmmrm128,ymmreg,imm8Convert eight single-precision floating point values in a YMM register to half-precision floating-point values in memory or an XMM register

FMA3

Supported in AMD processors starting with the Piledriver architecture and Intel starting with Haswell processors and Broadwell processors since 2014.

Fused multiply-add (floating-point vector multiply–accumulate) with three operands.

InstructionMeaning
VFMADD132PDFused Multiply-Add of Packed Double-Precision Floating-Point Values
VFMADD213PDFused Multiply-Add of Packed Double-Precision Floating-Point Values
VFMADD231PDFused Multiply-Add of Packed Double-Precision Floating-Point Values
VFMADD132PSFused Multiply-Add of Packed Single-Precision Floating-Point Values
VFMADD213PSFused Multiply-Add of Packed Single-Precision Floating-Point Values
VFMADD231PSFused Multiply-Add of Packed Single-Precision Floating-Point Values
VFMADD132SDFused Multiply-Add of Scalar Double-Precision Floating-Point Values
VFMADD213SDFused Multiply-Add of Scalar Double-Precision Floating-Point Values
VFMADD231SDFused Multiply-Add of Scalar Double-Precision Floating-Point Values
VFMADD132SSFused Multiply-Add of Scalar Single-Precision Floating-Point Values
VFMADD213SSFused Multiply-Add of Scalar Single-Precision Floating-Point Values
VFMADD231SSFused Multiply-Add of Scalar Single-Precision Floating-Point Values
VFMADDSUB132PDFused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
VFMADDSUB213PDFused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
VFMADDSUB231PDFused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
VFMADDSUB132PSFused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
VFMADDSUB213PSFused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
VFMADDSUB231PSFused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
VFMSUB132PDFused Multiply-Subtract of Packed Double-Precision Floating-Point Values
VFMSUB213PDFused Multiply-Subtract of Packed Double-Precision Floating-Point Values
VFMSUB231PDFused Multiply-Subtract of Packed Double-Precision Floating-Point Values
VFMSUB132PSFused Multiply-Subtract of Packed Single-Precision Floating-Point Values
VFMSUB213PSFused Multiply-Subtract of Packed Single-Precision Floating-Point Values
VFMSUB231PSFused Multiply-Subtract of Packed Single-Precision Floating-Point Values
VFMSUB132SDFused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
VFMSUB213SDFused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
VFMSUB231SDFused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
VFMSUB132SSFused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
VFMSUB213SSFused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
VFMSUB231SSFused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
VFMSUBADD132PDFused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
VFMSUBADD213PDFused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
VFMSUBADD231PDFused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
VFMSUBADD132PSFused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
VFMSUBADD213PSFused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
VFMSUBADD231PSFused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
VFNMADD132PDFused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
VFNMADD213PDFused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
VFNMADD231PDFused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
VFNMADD132PSFused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
VFNMADD213PSFused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
VFNMADD231PSFused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
VFNMADD132SDFused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
VFNMADD213SDFused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
VFNMADD231SDFused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
VFNMADD132SSFused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
VFNMADD213SSFused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
VFNMADD231SSFused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
VFNMSUB132PDFused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
VFNMSUB213PDFused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
VFNMSUB231PDFused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
VFNMSUB132PSFused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
VFNMSUB213PSFused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
VFNMSUB231PSFused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
VFNMSUB132SDFused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
VFNMSUB213SDFused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
VFNMSUB231SDFused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
VFNMSUB132SSFused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
VFNMSUB213SSFused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values
VFNMSUB231SSFused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values

FMA4

Supported in AMD processors starting with the Bulldozer architecture. Not supported by any intel chip as of 2017.

Fused multiply-add with four operands. FMA4 was realized in hardware before FMA3.

InstructionOpcodeMeaningNotes
VFMADDPD xmm0, xmm1, xmm2, xmm3C4E3 WvvvvL01 69 /r /is4Fused Multiply-Add of Packed Double-Precision Floating-Point Values
VFMADDPS xmm0, xmm1, xmm2, xmm3C4E3 WvvvvL01 68 /r /is4Fused Multiply-Add of Packed Single-Precision Floating-Point Values
VFMADDSD xmm0, xmm1, xmm2, xmm3C4E3 WvvvvL01 6B /r /is4Fused Multiply-Add of Scalar Double-Precision Floating-Point Values
VFMADDSS xmm0, xmm1, xmm2, xmm3C4E3 WvvvvL01 6A /r /is4Fused Multiply-Add of Scalar Single-Precision Floating-Point Values
VFMADDSUBPD xmm0, xmm1, xmm2, xmm3C4E3 WvvvvL01 5D /r /is4Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values
VFMADDSUBPS xmm0, xmm1, xmm2, xmm3C4E3 WvvvvL01 5C /r /is4Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values
VFMSUBADDPD xmm0, xmm1, xmm2, xmm3C4E3 WvvvvL01 5F /r /is4Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values
VFMSUBADDPS xmm0, xmm1, xmm2, xmm3C4E3 WvvvvL01 5E /r /is4Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values
VFMSUBPD xmm0, xmm1, xmm2, xmm3C4E3 WvvvvL01 6D /r /is4Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values
VFMSUBPS xmm0, xmm1, xmm2, xmm3C4E3 WvvvvL01 6C /r /is4Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
VFMSUBSD xmm0, xmm1, xmm2, xmm3C4E3 WvvvvL01 6F /r /is4Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
VFMSUBSS xmm0, xmm1, xmm2, xmm3C4E3 WvvvvL01 6E /r /is4Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
VFNMADDPD xmm0, xmm1, xmm2, xmm3C4E3 WvvvvL01 79 /r /is4Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values
VFNMADDPS xmm0, xmm1, xmm2, xmm3C4E3 WvvvvL01 78 /r /is4Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values
VFNMADDSD xmm0, xmm1, xmm2, xmm3C4E3 WvvvvL01 7B /r /is4Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values
VFNMADDSS xmm0, xmm1, xmm2, xmm3C4E3 WvvvvL01 7A /r /is4Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values
VFNMSUBPD xmm0, xmm1, xmm2, xmm3C4E3 WvvvvL01 7D /r /is4Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values
VFNMSUBPS xmm0, xmm1, xmm2, xmm3C4E3 WvvvvL01 7C /r /is4Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values
VFNMSUBSD xmm0, xmm1, xmm2, xmm3C4E3 WvvvvL01 7F /r /is4Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values
VFNMSUBSS xmm0, xmm1, xmm2, xmm3C4E3 WvvvvL01 7E /r /is4Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values

AVX

AVX were first supported by Intel with Sandy Bridge and by AMD with Bulldozer.

Vector operations on 256 bit registers.

Instruction Description
VBROADCASTSS Copy a 32-bit, 64-bit or 128-bit memory operand to all elements of a XMM or YMM vector register.
VBROADCASTSD
VBROADCASTF128
VINSERTF128 Replaces either the lower half or the upper half of a 256-bit YMM register with the value of a 128-bit source operand. The other half of the destination is unchanged.
VEXTRACTF128 Extracts either the lower half or the upper half of a 256-bit YMM register and copies the value to a 128-bit destination operand.
VMASKMOVPS Conditionally reads any number of elements from a SIMD vector memory operand into a destination register, leaving the remaining vector elements unread and setting the corresponding elements in the destination register to zero. Alternatively, conditionally writes any number of elements from a SIMD vector register operand to a vector memory operand, leaving the remaining elements of the memory operand unchanged. On the AMD Jaguar processor architecture, this instruction with a memory source operand takes more than 300 clock cycles when the mask is zero, in which case the instruction should do nothing. This appears to be a design flaw.[12]
VMASKMOVPD
VPERMILPS Permute In-Lane. Shuffle the 32-bit or 64-bit vector elements of one input operand. These are in-lane 256-bit instructions, meaning that they operate on all 256 bits with two separate 128-bit shuffles, so they can not shuffle across the 128-bit lanes.[13]
VPERMILPD
VPERM2F128 Shuffle the four 128-bit vector elements of two 256-bit source operands into a 256-bit destination operand, with an immediate constant as selector.
VZEROALL Set all YMM registers to zero and tag them as unused. Used when switching between 128-bit use and 256-bit use.
VZEROUPPER Set the upper half of all YMM registers to zero. Used when switching between 128-bit use and 256-bit use.

AVX2

Introduced in Intel's Haswell microarchitecture and AMD's Excavator.

Expansion of most vector integer SSE and AVX instructions to 256 bits

Instruction Description
VBROADCASTSS Copy a 32-bit or 64-bit register operand to all elements of a XMM or YMM vector register. These are register versions of the same instructions in AVX1. There is no 128-bit version however, but the same effect can be simply achieved using VINSERTF128.
VBROADCASTSD
VPBROADCASTB Copy an 8, 16, 32 or 64-bit integer register or memory operand to all elements of a XMM or YMM vector register.
VPBROADCASTW
VPBROADCASTD
VPBROADCASTQ
VBROADCASTI128 Copy a 128-bit memory operand to all elements of a YMM vector register.
VINSERTI128 Replaces either the lower half or the upper half of a 256-bit YMM register with the value of a 128-bit source operand. The other half of the destination is unchanged.
VEXTRACTI128 Extracts either the lower half or the upper half of a 256-bit YMM register and copies the value to a 128-bit destination operand.
VGATHERDPD Gathers single or double precision floating point values using either 32 or 64-bit indices and scale.
VGATHERQPD
VGATHERDPS
VGATHERQPS
VPGATHERDD Gathers 32 or 64-bit integer values using either 32 or 64-bit indices and scale.
VPGATHERDQ
VPGATHERQD
VPGATHERQQ
VPMASKMOVD Conditionally reads any number of elements from a SIMD vector memory operand into a destination register, leaving the remaining vector elements unread and setting the corresponding elements in the destination register to zero. Alternatively, conditionally writes any number of elements from a SIMD vector register operand to a vector memory operand, leaving the remaining elements of the memory operand unchanged.
VPMASKMOVQ
VPERMPS Shuffle the eight 32-bit vector elements of one 256-bit source operand into a 256-bit destination operand, with a register or memory operand as selector.
VPERMD
VPERMPD Shuffle the four 64-bit vector elements of one 256-bit source operand into a 256-bit destination operand, with a register or memory operand as selector.
VPERMQ
VPERM2I128 Shuffle (two of) the four 128-bit vector elements of two 256-bit source operands into a 256-bit destination operand, with an immediate constant as selector.
VPBLENDD Doubleword immediate version of the PBLEND instructions from SSE4.
VPSLLVD Shift left logical. Allows variable shifts where each element is shifted according to the packed input.
VPSLLVQ
VPSRLVD Shift right logical. Allows variable shifts where each element is shifted according to the packed input.
VPSRLVQ
VPSRAVD Shift right arithmetically. Allows variable shifts where each element is shifted according to the packed input.

AVX-512

Introduced in Intel's Xeon Phi x200

Vector operations on 512 bit registers.

AVX-512 foundation
Instruction Description
VBLENDMPD Blend float64 vectors using opmask control
VBLENDMPS Blend float32 vectors using opmask control
VPBLENDMD Blend int32 vectors using opmask control
VPBLENDMQ Blend int64 vectors using opmask control
VPCMPD Compare signed/unsigned doublewords into mask
VPCMPUD
VPCMPQ Compare signed/unsigned quadwords into mask
VPCMPUQ
VPTESTMD Logical AND and set mask for 32 or 64 bit integers.
VPTESTMQ
VPTESTNMD Logical NAND and set mask for 32 or 64 bit integers.
VPTESTNMQ
VCOMPRESSPD Store sparse packed double/single-precision floating-point values into dense memory
VCOMPRESSPS
VPCOMPRESSD Store sparse packed doubleword/quadword integer values into dense memory/register
VPCOMPRESSQ
VEXPANDPD Load sparse packed double/single-precision floating-point values from dense memory
VEXPANDPS
VPEXPANDD Load sparse packed doubleword/quadword integer values from dense memory/register
VPEXPANDQ
VPERMI2PD Full single/double floating point permute overwriting the index.
VPERMI2PS
VPERMI2D Full doubleword/quadword permute overwriting the index.
VPERMI2Q
VPERMT2PS Full single/double floating point permute overwriting first source.
VPERMT2PD
VPERMT2D Full doubleword/quadword permute overwriting first source.
VPERMT2Q
VSHUFF32x4 Shuffle four packed 128-bit lines.
VSHUFF64x2
VSHUFFI32x4
VSHUFFI64x2
VPTERNLOGD Bitwise Ternary Logic
VPTERNLOGQ
VPMOVQD Down convert quadword or doubleword to doubleword, word or byte; unsaturated, saturated or saturated unsigned. The reverse of the sign/zero extend instructions from SSE4.1.
VPMOVSQD
VPMOVUSQD
VPMOVQW
VPMOVSQW
VPMOVUSQW
VPMOVQB
VPMOVSQB
VPMOVUSQB
VPMOVDW
VPMOVSDW
VPMOVUSDW
VPMOVDB
VPMOVSDB
VPMOVUSDB
VCVTPS2UDQ Convert with or without truncation, packed single or double-precision floating point to packed unsigned doubleword integers.
VCVTPD2UDQ
VCVTTPS2UDQ
VCVTTPD2UDQ
VCVTSS2USI Convert with or without trunction, scalar single or double-precision floating point to unsigned doubleword integer.
VCVTSD2USI
VCVTTSS2USI
VCVTTSD2USI
VCVTUDQ2PS Convert packed unsigned doubleword integers to packed single or double-precision floating point.
VCVTUDQ2PD
VCVTUSI2PS Convert scalar unsigned doubleword integers to single or double-precision floating point.
VCVTUSI2PD
VCVTUSI2SD Convert scalar unsigned integers to single or double-precision floating point.
VCVTUSI2SS
VCVTQQ2PD Convert packed quadword integers to packed single or double-precision floating point.
VCVTQQ2PS
VGETEXPPD Convert exponents of packed fp values into fp values
VGETEXPPS
VGETEXPSD Convert exponent of scalar fp value into fp value
VGETEXPSS
VGETMANTPD Extract vector of normalized mantissas from float32/float64 vector
VGETMANTPS
VGETMANTSD Extract float32/float64 of normalized mantissa from float32/float64 scalar
VGETMANTSS
VFIXUPIMMPD Fix up special packed float32/float64 values
VFIXUPIMMPS
VFIXUPIMMSD Fix up special scalar float32/float64 value
VFIXUPIMMSS
VRCP14PD Compute approximate reciprocals of packed float32/float64 values
VRCP14PS
VRCP14SD Compute approximate reciprocals of scalar float32/float64 value
VRCP14SS
VRNDSCALEPS Round packed float32/float64 values to include a given number of fraction bits
VRNDSCALEPD
VRNDSCALESS Round scalar float32/float64 value to include a given number of fraction bits
VRNDSCALESD
VRSQRT14PD Compute approximate reciprocals of square roots of packed float32/float64 values
VRSQRT14PS
VRSQRT14SD Compute approximate reciprocal of square root of scalar float32/float64 value
VRSQRT14SS
VSCALEFPS Scale packed float32/float64 values with float32/float64 values
VSCALEFPD
VSCALEFSS Scale scalar float32/float64 value with float32/float64 value
VSCALEFSD
VALIGND Align doubleword or quadword vectors
VALIGNQ
VPABSQ Packed absolute value quadword
VPMAXSQ Maximum of packed signed/unsigned quadword
VPMAXUQ
VPMINSQ Minimum of packed signed/unsigned quadword
VPMINUQ
VPROLD Bit rotate left or right
VPROLVD
VPROLQ
VPROLVQ
VPRORD
VPRORVD
VPRORQ
VPRORVQ
VPSCATTERDD Scatter packed doubleword/quadword with signed doubleword and quadword indices
VPSCATTERDQ
VPSCATTERQD
VPSCATTERQQ
VSCATTERDPS Scatter packed float32/float64 with signed doubleword and quadword indices
VSCATTERDPD
VSCATTERQPS
VSCATTERQPD

Cryptographic instructions

Intel AES instructions
Main article: AES instruction set

6 new instructions.

Instruction Description
AESENC Perform one round of an AES encryption flow
AESENCLAST Perform the last round of an AES encryption flow
AESDEC Perform one round of an AES decryption flow
AESDECLAST Perform the last round of an AES decryption flow
AESKEYGENASSIST Assist in AES round key generation
AESIMC Assist in AES Inverse Mix Columns

RDRAND and RDSEED
Main article: RDRAND
Instruction Description
RDRAND Read Random Number
RDSEED Read Random Seed

Intel SHA instructions
Main article: Intel SHA extensions

7 new instructions.

Instruction Description
SHA1RNDS4 Perform Four Rounds of SHA1 Operation
SHA1NEXTE Calculate SHA1 State Variable E after Four Rounds
SHA1MSG1 Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords
SHA1MSG2 Perform a Final Calculation for the Next Four SHA1 Message Dwords
SHA256RNDS2 Perform Two Rounds of SHA256 Operation
SHA256MSG1 Perform an Intermediate Calculation for the Next Four SHA256 Message Dwords
SHA256MSG2 Perform a Final Calculation for the Next Four SHA256 Message Dwords

Undocumented instructions

Undocumented x86 instructions

The x86 CPUs contain undocumented instructions which are implemented on the chips but not listed in some official documents. They can be found in various sources across the Internet, such as Ralf Brown's Interrupt List and at sandpile.org

Mnemonic Opcode Description Status
AAM imm8 D4 imm8 Divide AL by imm8, put the quotient in AH, and the remainder in AL Available beginning with 8086, documented since Pentium (earlier documentation lists no arguments)
AAD imm8 D5 imm8 Multiplication counterpart of AAM Available beginning with 8086, documented since Pentium (earlier documentation lists no arguments)
SALC D6 Set AL depending on the value of the Carry Flag (a 1-byte alternative of SBB AL, AL) Available beginning with 8086, but only documented since Pentium Pro.
ICEBP F1 Single byte single-step exception / Invoke ICE Available beginning with 80386, documented (as INT1) since Pentium Pro
Unknown mnemonic 0F 04 Exact purpose unknown, causes CPU hang (HCF). The only way out is CPU reset.[14]

In some implementations, emulated through BIOS as a halting sequence.[15]

In a forum post at the Vintage Computing Federation, this instruction is explained as SAVEALL. It interacts with ICE mode.

 Only available on 80286
LOADALL 0F 05 Loads All Registers from Memory Address 0x000800H Only available on 80286
LOADALLD 0F 07 Loads All Registers from Memory Address ES:EDI Only available on 80386
UD1 0F B9 Intentionally undefined instruction, but unlike UD2 this was not published
ALTINST 0F 3F Jump and execute instructions in the undocumented Alternate Instruction Set. Only available on some x86 processors made by VIA Technologies.

Undocumented x87 instructions

FFREEP performs FFREE ST(i) and pop stack

See also

References
  1. "Re: Intel Processor Identification and the CPUID Instruction". Retrieved 2013-04-21.
  2. Toth, Ervin (1998-03-16). "BSWAP with 16-bit registers". Archived from the original on 1999-11-03. The instruction brings down the upper word of the doubleword register without affecting its upper 16 bits.
  3. Coldwin, Gynvael (2009-12-29). "BSWAP + 66h prefix". Retrieved 2018-10-03. internal (zero-)extending the value of a smaller (16-bit) register … applying the bswap to a 32-bit value "00 00 AH AL", … truncated to lower 16-bits, which are "00 00". … Bochs … bswap reg16 acts just like the bswap reg32 … QEMU … ignores the 66h prefix
  4. "RSM—Resume from System Management Mode". Archived from the original on 2012-03-12.CS1 maint: bot: original URL status unknown (link)
  5. Intel 64 and IA-32 Architectures Optimization Reference Manual, section 7.3.2
  6. Intel 64 and IA-32 Architectures Software Developer’s Manual, section 4.3, subsection "PREFETCHh—Prefetch Data Into Caches"
  7. Hollingsworth, Brent. "New "Bulldozer" and "Piledriver" instructions" (pdf). Advanced Micro Devices, Inc. Retrieved 11 December 2014.
  8. "Family 16h AMD A-Series Data Sheet" (PDF). amd.com. AMD. October 2013. Retrieved 2014-01-02.
  9. "AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions" (PDF). amd.com. AMD. October 2013. Retrieved 2014-01-02.
  10. "tbmintrin.h from GCC 4.8". Retrieved 2014-03-17.
  11. https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf section 3.5.2.3
  12. "The microarchitecture of Intel, AMD and VIA CPUs: An optimization guide for assembly programmers and compiler makers" (PDF). Retrieved October 17, 2016.
  13. "Chess programming AVX2". Retrieved October 17, 2016.
  14. "Re: Undocumented opcodes (HINT_NOP)". Archived from the original on 2004-11-06. Retrieved 2010-11-07.
  15. "Re: Also some undocumented 0Fh opcodes". Archived from the original on 2003-06-26. Retrieved 2010-11-07.
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